From: Richard Henderson <richard.henderson@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps
Date: Fri, 29 Oct 2021 12:36:35 -0700 [thread overview]
Message-ID: <59907aa4-4b40-9f02-e87c-18e7fc2dc460@linaro.org> (raw)
In-Reply-To: <20211029152535.2055096-3-bin.meng@windriver.com>
On 10/29/21 8:25 AM, Bin Meng wrote:
> +void riscv_cpu_debug_excp_handler(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (cs->watchpoint_hit) {
> + if (cs->watchpoint_hit->flags & BP_CPU) {
> + cs->watchpoint_hit = NULL;
> + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC());
> + }
> + } else {
> + if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
> + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC());
> + }
> + }
> +}
GETPC is only to be used by handlers called from TCG generated code.
You want 0 to indicate that unwinding is not needed, as it has been done for you already
by generic code.
r~
next prev parent reply other threads:[~2021-10-29 20:10 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 15:25 [PATCH 0/5] target/riscv: Initial support for native debug feature via M-mode CSRs Bin Meng
2021-10-29 15:25 ` [PATCH 1/5] target/riscv: Add initial support for native debug Bin Meng
2021-10-29 19:41 ` Richard Henderson
2021-10-29 15:25 ` [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2021-10-29 19:36 ` Richard Henderson [this message]
2021-10-29 15:25 ` [PATCH 3/5] target/riscv: Add a config option for native debug Bin Meng
2021-10-29 19:34 ` Richard Henderson
2021-10-29 15:25 ` [PATCH 4/5] target/riscv: csr: Hook debug CSR read/write Bin Meng
2021-10-29 15:25 ` [PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2021-10-29 19:33 ` Richard Henderson
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