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[83.193.250.196]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f25a0fa1esm2172849f8f.100.2025.02.13.07.45.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Feb 2025 07:45:32 -0800 (PST) Message-ID: <59d1bd38-2b0f-413a-a6ff-28f8a055dad0@linaro.org> Date: Thu, 13 Feb 2025 16:45:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] tcg: Introduce the 'z' constraint for a hardware zero register To: Richard Henderson , qemu-devel@nongnu.org References: <20250212034617.1079324-1-richard.henderson@linaro.org> <20250212034617.1079324-2-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250212034617.1079324-2-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/2/25 04:46, Richard Henderson wrote: > For loongarch, mips, riscv and sparc, a zero register is > available all the time. For aarch64, register index 31 > depends on context: sometimes it is the stack pointer, > and sometimes it is the zero register. > > Introduce a new general-purpose constraint which maps 0 > to TCG_REG_ZERO, if defined. This differs from existing > constant constraints in that const_arg[*] is recorded as > false, indicating that the value is in a register. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg.h | 3 ++- > tcg/aarch64/tcg-target.h | 2 ++ > tcg/loongarch64/tcg-target.h | 2 ++ > tcg/mips/tcg-target.h | 2 ++ > tcg/riscv/tcg-target.h | 2 ++ > tcg/sparc64/tcg-target.h | 3 ++- > tcg/tcg.c | 29 ++++++++++++++++++++++------- > docs/devel/tcg-ops.rst | 4 +++- > 8 files changed, 37 insertions(+), 10 deletions(-) > diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst > index 6608a29376..75acb4bd32 100644 > --- a/docs/devel/tcg-ops.rst > +++ b/docs/devel/tcg-ops.rst > @@ -927,7 +927,9 @@ operation uses a constant input constraint which does not allow all > constants, it must also accept registers in order to have a fallback. > The constraint '``i``' is defined generically to accept any constant. > The constraint '``r``' is not defined generically, but is consistently > -used by each backend to indicate all registers. > +used by each backend to indicate all registers. If ``TCG_REG_ZERO`` > +is defined by the backend, the constraint '``z``' is defined generically and/to? > +map 0 to the hardware zero register. > > The movi_i32 and movi_i64 operations must accept any constants. > Reviewed-by: Philippe Mathieu-Daudé