From: Richard Henderson <richard.henderson@linaro.org>
To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: Re: [RFC 05/15] target/riscv: rvb: pack two words into one register
Date: Thu, 19 Nov 2020 11:43:52 -0800 [thread overview]
Message-ID: <59f30d7e-dcdd-6a7b-1de9-ec07f621c9fa@linaro.org> (raw)
In-Reply-To: <20201118083044.13992-6-frank.chang@sifive.com>
On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> +#ifdef TARGET_RISCV64
> + tcg_gen_ext32u_tl(lower, arg1);
> + tcg_gen_shli_tl(higher, arg2, 32);
> +#else
> + tcg_gen_ext16u_tl(lower, arg1);
> + tcg_gen_shli_tl(higher, arg2, 16);
> +#endif
> +
tcg_gen_deposit(ret, arg1, arg2,
TARGET_LONG_BITS / 2,
TARGET_LONG_BITS / 2);
> +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> +#ifdef TARGET_RISCV64
> + tcg_gen_shri_tl(lower, arg1, 32);
> + tcg_gen_shri_tl(higher, arg2, 32);
> + tcg_gen_shli_tl(higher, higher, 32);
> +#else
> + tcg_gen_shri_tl(lower, arg1, 16);
> + tcg_gen_shri_tl(higher, arg2, 16);
> + tcg_gen_shli_tl(higher, higher, 16);
> +#endif
> +
> + tcg_gen_or_tl(ret, higher, lower);
tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
> +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> + tcg_gen_ext8u_tl(lower, arg1);
> + tcg_gen_ext8u_tl(higher, arg2);
> + tcg_gen_shli_tl(higher, higher, 8);
> +
> + tcg_gen_or_tl(ret, higher, lower);
tcg_gen_ext8u_tl(t, arg2);
tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
> +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> + tcg_gen_ext16u_tl(lower, arg1);
> + tcg_gen_shli_tl(higher, arg2, 16);
> + tcg_gen_or_tl(ret, higher, lower);
> +
> + tcg_gen_ext32s_tl(ret, ret);
> +
> + tcg_temp_free(lower);
> + tcg_temp_free(higher);
> +}
tcg_gen_ext16s_i64(t, arg2);
tcg_gen_deposit_i64(ret, arg1, t, 16, 48);
> +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv lower, higher;
> + lower = tcg_temp_new();
> + higher = tcg_temp_new();
> +
> + tcg_gen_shri_tl(lower, arg1, 16);
> + tcg_gen_shri_tl(higher, arg2, 16);
> + tcg_gen_shli_tl(higher, higher, 16);
> + tcg_gen_or_tl(ret, higher, lower);
> +
> + tcg_gen_ext32s_tl(ret, ret);
tcg_gen_shri_i64(t, arg1, 16);
tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
tcg_gen_ext32s_i64(ret, ret);
r~
next prev parent reply other threads:[~2020-11-19 19:44 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-18 8:29 [RFC 00/15] support subsets of bitmanip extension frank.chang
2020-11-18 8:29 ` [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension frank.chang
2020-11-19 19:03 ` Richard Henderson
2020-11-18 8:29 ` [RFC 02/15] target/riscv: rvb: count leading/trailing zeros frank.chang
2020-11-19 19:24 ` Richard Henderson
2020-11-19 19:48 ` Richard Henderson
2020-11-18 8:29 ` [RFC 03/15] target/riscv: rvb: count bits set frank.chang
2020-11-19 19:27 ` Richard Henderson
2020-11-18 8:29 ` [RFC 04/15] target/riscv: rvb: logic-with-negate frank.chang
2020-11-19 19:28 ` Richard Henderson
2020-11-18 8:29 ` [RFC 05/15] target/riscv: rvb: pack two words into one register frank.chang
2020-11-19 19:43 ` Richard Henderson [this message]
2020-11-18 8:29 ` [RFC 06/15] target/riscv: rvb: min/max instructions frank.chang
2020-11-19 19:46 ` Richard Henderson
2020-11-18 8:29 ` [RFC 07/15] target/riscv: rvb: sign-extend instructions frank.chang
2020-11-19 19:48 ` Richard Henderson
2020-11-18 8:29 ` [RFC 08/15] target/riscv: rvb: single-bit instructions frank.chang
2020-11-19 20:05 ` Richard Henderson
2020-11-19 20:35 ` Richard Henderson
2020-11-19 21:04 ` Richard Henderson
2020-12-04 17:10 ` Frank Chang
2020-11-18 8:29 ` [RFC 09/15] target/riscv: rvb: shift ones frank.chang
2020-11-19 20:54 ` Richard Henderson
2020-11-18 8:29 ` [RFC 10/15] target/riscv: rvb: rotate (left/right) frank.chang
2020-11-19 21:06 ` Richard Henderson
2020-11-18 8:29 ` [RFC 11/15] target/riscv: rvb: generalized reverse frank.chang
2020-11-19 21:24 ` Richard Henderson
2020-11-18 8:29 ` [RFC 12/15] target/riscv: rvb: generalized or-combine frank.chang
2020-11-19 21:28 ` Richard Henderson
2020-11-18 8:29 ` [RFC 13/15] target/riscv: rvb: address calculation frank.chang
2020-11-19 21:38 ` Richard Henderson
2020-11-18 8:29 ` [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend frank.chang
2020-11-19 22:15 ` Richard Henderson
2020-11-18 8:29 ` [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2020-11-19 18:54 ` Alistair Francis
2020-11-20 3:02 ` Kito Cheng
2020-11-20 16:24 ` Alistair Francis
2020-11-23 1:22 ` Frank Chang
2020-11-19 22:26 ` [RFC 00/15] support subsets of bitmanip extension Richard Henderson
2020-11-20 1:45 ` Frank Chang
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