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charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=shentey@gmail.com; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 27=2E Juni 2023 07:11:33 UTC schrieb Paolo Bonzini : >On 6/26/23 23:19, Olaf Hering wrote: >> I need advice on how to debug this=2E >>=20 >> One thing that stands out is uhci_irq()=2E >> It reads a u16 from the USBSTS register=2E >>=20 >> On the qemu side, this read is served from bmdma_read=2E Since the read >> size is 2, the result is ~0, and uhci_irq() turns the controller off=2E >> In other words, memory_region_ops_read from addr=3D0xc102 is served fro= m "piix-bmdma" >>=20 >> If the pci_set_word calls in piix_ide_reset are skipped, the read is >> served from uhci_port_write=2E This is the expected behavior=2E >> In other words, memory_region_ops_read from addr=3D0xc102 is served fro= m "uhci"=2E > >I think what's happening is that > > pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */ > >is setting the BAR to 0xC100, therefore overlapping the UHCI device's reg= ion=2E In principle this line shouldn't be necessary at all though; it's e= nough to clear the COMMAND register=2E Interesting=2E The BAR is a 32 bit register whose default value is 0x00000= 001=2E I think what's supposed to happen here is a pci_set_long() rather th= an a pci_set_byte()=2E Bits 4=2E=2E15 represent the BAR address, and pci_set_byte() only clears b= its 4=2E=2E7, leaving bits 8=2E=2E15 unchanged=2E Perhaps this causes the B= AR to be moved into the UHCI region? Does changing the call to pci_set_long= () fix the problem? Best regards, Bernhard > >Can you check the value of the COMMAND register (pci_conf + 0x04, 16 bits= , little endian)? Something might be causing the register to be set back t= o a nonzero value, therefore re-enabling the I/O at the address that overla= ps the UHCI device=2E > >Paolo > >