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[77.191.68.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c89e1cesm1609195f8f.64.2024.12.19.06.16.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Dec 2024 06:16:22 -0800 (PST) Date: Thu, 19 Dec 2024 14:16:20 +0000 From: Bernhard Beschow To: BALATON Zoltan , Phil Dennis-Jordan CC: Nicholas Piggin , qemu-devel@nongnu.org, Akihiko Odaki , =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v2_1/2=5D_hw/usb/hcd-xhci-p?= =?US-ASCII?Q?ci=3A_Make_PCI_device_more_configurable?= In-Reply-To: References: <20241212085207.1439501-1-npiggin@gmail.com> <20241212085207.1439501-2-npiggin@gmail.com> Message-ID: <5FF37BC7-D27E-439C-97CA-D3E397056404@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=shentey@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 19=2E Dezember 2024 09:23:13 UTC schrieb BALATON Zoltan : >On Wed, 18 Dec 2024, Phil Dennis-Jordan wrote: >> On Wed, 18 Dec 2024 at 02:19, Nicholas Piggin wro= te: >>> On Thu Dec 12, 2024 at 8:41 PM AEST, Phil Dennis-Jordan wrote: >>>> Hey Nicholas, >>>>=20 >>>> I'm not an XHCI & PCI expert (yet?) so apologies if I've got some of = this >>>> wrong, but I've asked some questions and made some comments inline: >>>=20 >>> Hey Phil, >>>=20 >>> Thanks for the review, looks like you are the expert now :) >>>=20 >>=20 >> The "hot potato" method for determining maintainership=2E :-) > >That's how I got some parts I'm maintainer of now=2E :-) > >[=2E=2E=2E] >>>> On Thu, 12 Dec 2024 at 09:52, Nicholas Piggin w= rote: >>>> Surely we should only propagate the error and fail realize() iff s->m= six >>> is >>>> ON_OFF_AUTO_ON? >>>>=20 >>>> For ON_OFF_AUTO_AUTO, msix_init returning failure isn't a critical er= ror=2E >>>=20 >>> Yep you're right=2E=2E=2E you had been testing with msix disabled=2E I= wonder if >>> there is a good way to force fail this in qtests? >>>=20 >>=20 >> I'm really the wrong person to ask about qtest, I'm only just beginning= to >> get to grips with it=2E It seems the only real reason msix_init fails o= ther >> than misconfiguration of the device/BAR is when msi_nonbroken =3D false= =2E >>=20 >> At least on x86(-64), msi_nonbroken=3Dtrue is unconditionally set in >> apic_realize()=2E (I think real hardware would not support MSI(-X) on t= he >> i440FX chipset - I was fairly certain it was the PCI root/southbridge >> catching the writes to the reserved memory region, and I didn't think t= he >> PIIX did this; but at least in QEMU it doesn't seem to be implemented i= n a >> chipset-dependent way=2E) I'm not sure it's possible to run QEMU withou= t an >> APIC? > >There's isapc but you can't attach PCI card to that=2E It seems according= to -machine pc,help that there's a PIC=3D option but no similar= for APIC=2E Maybe that could be added but not sure it would work=2E (Addin= g Bernhard to cc to quickly pass on the potato=2E) I agree, the only x86 machine with no APIC is the isapc machine=2E All oth= ers (i440fx, q35, microvm) have it always enabled=2E I guess there is just = no point in disabling it since the APIC is part of the architecture for age= s and SMP requires it=2E Although PIIX3+ didn't have an APIC built-in it ha= d interfaces for handling a dedicated one which is basically what QEMU emul= ates=2E Best regards, Bernhard > >Regards, >BALATON Zoltan > >> On aarch64, the GICv3 needs to explicitly enable support (via the ITS),= so >> perhaps it's possible to set up an aarch64 qtest with ITS disabled? It >> looks like the 'virt' machine type only supports the ITS from version 6= =2E2, >> so older versions will disable it=2E >>=20 >> Sorry, clutching at straws here=2E >>=20 >>=20 >>>>> + >>>>> + pci_register_bar(dev, s->msix_bar_nr, >>>>> + PCI_BASE_ADDRESS_SPACE_MEMORY | >>>>> + PCI_BASE_ADDRESS_MEM_TYPE_64, >>>>> + msix_bar); >>>>>=20 >>>>=20 >>>> Is it safe to call pci_register_bar() again for the msix_bar_nr =3D 0= case? >>>> Even if it is safe, is it sensible? If we're calling it twice for the >>> same >>>> BAR, and the arguments of either of the calls changes in future, the >>> other >>>> needs to change too=2E Doesn't seem ideal=2E >>>=20 >>> Good catch=2E It looks like it "works" so long as the bar wasn't mappe= d, >>> but I'm sure bad practice=2E=2E=2E Interesting there is no assertion i= n >>> there though=2E I'll fix it though=2E >>>=20 >>=20 >> I notice there's a msix_init_exclusive_bar()=E2=80=A6 I wonder if it'd = be simpler >> to use that and modify it so it allows you to choose a size and layout = for >> the BAR, rather than adding all that extra code to deal with the extra = BAR >> in the XHCI? >> (It already calls pci_register_bar() and msix_init() internally, but se= ems >> to set the BAR's size to 4096 and places the PBA at halfway through the >> BAR=2E Perhaps rename it to something like >> msix_init_exclusive_bar_with_layout and pass the bar_size and >> bar_pba_offset in as parameters; then make msix_init_exclusive_bar() a >> wrapper for that function with the existing defaults for those variable= s?) >>=20 >> Just kicking around some ideas here, I have no idea if that actually en= ds >> up making things simpler=E2=80=A6 >>=20 >>=20 >>> Thanks, >>> Nick >>>=20 >>