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Tsirkin" , Marcel Apfelbaum References: <20240731170019.3590563-1-peter.maydell@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240731170019.3590563-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 31/7/24 19:00, Peter Maydell wrote: > In amdvi_update_iotlb() we will only put a new entry in the hash > table if to_cache.perm is not IOMMU_NONE. However we allocate the > memory for the new AMDVIIOTLBEntry and for the hash table key > regardless. This means that in the IOMMU_NONE case we will leak the > memory we alloacted. > > Move the allocations into the if() to the point where we know we're > going to add the item to the hash table. > > Cc: qemu-stable@nongnu.org > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2452 > Signed-off-by: Peter Maydell > --- > Tested with 'make check' and 'make check-avocado' only, but the > bug and fix seem straightforward... Oh now I remembered: https://lore.kernel.org/qemu-devel/CACGkMEtjmpX8G9HYZ0r3n5ErhAENKhQ81f4ocfCYrh=XoF=5hw@mail.gmail.com/ > --- > hw/i386/amd_iommu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 6d4fde72f9b..87643d28917 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -357,12 +357,12 @@ static void amdvi_update_iotlb(AMDVIState *s, uint16_t devid, > uint64_t gpa, IOMMUTLBEntry to_cache, > uint16_t domid) > { > - AMDVIIOTLBEntry *entry = g_new(AMDVIIOTLBEntry, 1); > - uint64_t *key = g_new(uint64_t, 1); > - uint64_t gfn = gpa >> AMDVI_PAGE_SHIFT_4K; > - > /* don't cache erroneous translations */ > if (to_cache.perm != IOMMU_NONE) { > + AMDVIIOTLBEntry *entry = g_new(AMDVIIOTLBEntry, 1); > + uint64_t *key = g_new(uint64_t, 1); > + uint64_t gfn = gpa >> AMDVI_PAGE_SHIFT_4K; > + > trace_amdvi_cache_update(domid, PCI_BUS_NUM(devid), PCI_SLOT(devid), > PCI_FUNC(devid), gpa, to_cache.translated_addr); >