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Thu, 24 Mar 2022 13:47:13 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D487FA4054; Thu, 24 Mar 2022 13:47:12 +0000 (GMT) Received: from [9.145.154.27] (unknown [9.145.154.27]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 24 Mar 2022 13:47:12 +0000 (GMT) Message-ID: <5a482e34-cadc-571a-360a-fb5ede7d8a2d@linux.ibm.com> Date: Thu, 24 Mar 2022 14:47:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/2] pcie: Don't try triggering a LSI when not defined Content-Language: en-US To: Daniel Henrique Barboza , clg@kaod.org, mst@redhat.com, marcel.apfelbaum@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20220321153357.165775-1-fbarrat@linux.ibm.com> <20220321153357.165775-2-fbarrat@linux.ibm.com> From: Frederic Barrat In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: dd2EeCJQwOj5mrRlri5zI_wegCItJ9zU X-Proofpoint-ORIG-GUID: yGBJBZaDPj5DBOhNXYnf6ZE5dW8mrpA4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-24_04,2022-03-24_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203240077 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 24/03/2022 14:07, Daniel Henrique Barboza wrote: > > > On 3/21/22 12:33, Frederic Barrat wrote: >> This patch skips [de]asserting a LSI interrupt if the device doesn't >> have any LSI defined. Doing so would trigger an assert in >> pci_irq_handler(). >> >> The PCIE root port implementation in qemu requests a LSI (INTA), but a >> subclass may want to change that behavior since it's a valid >> configuration. For example on the POWER8/POWER9/POWER10 systems, the >> root bridge doesn't request any LSI. >> >> Signed-off-by: Frederic Barrat >> --- > > I assume that it's easier to handle just the codepaths that powernv PHBs > uses > rather than handling all instances where pci_irq_handler() would be > asserting > without LSIs. The real reason is that the LSI is added when we realize the TYPE_PCIE_ROOT_PORT object. See rp_realize(). So I'm only trying to fix the code paths that can be called from a subclass of TYPE_PCIE_ROOT_PORT which would choose to override the "interrupt pin" setting in the config space. I believe they are all covered by this patch. The assert() in pci_irq_handler() is there for a reason and I don't want to mess with that. Fred > > > Patch LGTM. Small nits below: > >>   hw/pci/pcie.c     | 8 ++++++-- >>   hw/pci/pcie_aer.c | 4 +++- >>   2 files changed, 9 insertions(+), 3 deletions(-) >> >> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c >> index 67a5d67372..71c5194b80 100644 >> --- a/hw/pci/pcie.c >> +++ b/hw/pci/pcie.c >> @@ -354,7 +354,9 @@ static void hotplug_event_notify(PCIDevice *dev) >>       } else if (msi_enabled(dev)) { >>           msi_notify(dev, pcie_cap_flags_get_vector(dev)); >>       } else { >> -        pci_set_irq(dev, dev->exp.hpev_notified); >> +        if (pci_intx(dev) != -1) { >> +            pci_set_irq(dev, dev->exp.hpev_notified); >> +        } > > > Since you're not doing anything unless the condition is met, you can use > 'else if' > like it's done in the other conditionals: > > >     if (msix_enabled(dev)) { >         msix_notify(dev, pcie_cap_flags_get_vector(dev)); >     } else if (msi_enabled(dev)) { >         msi_notify(dev, pcie_cap_flags_get_vector(dev)); >     } else if (pci_intx(dev) != -1) { >         pci_set_irq(dev, dev->exp.hpev_notified); >     } > > > >>       } >>   } >> @@ -362,7 +364,9 @@ static void hotplug_event_clear(PCIDevice *dev) >>   { >>       hotplug_event_update_event_status(dev); >>       if (!msix_enabled(dev) && !msi_enabled(dev) && >> !dev->exp.hpev_notified) { >> -        pci_irq_deassert(dev); >> +        if (pci_intx(dev) != -1) { >> +            pci_irq_deassert(dev); >> +        } >>       } > > Similar comment here: > >     if (!msix_enabled(dev) && !msi_enabled(dev) && > !dev->exp.hpev_notified && >         pci_intx(dev) != -1) { >         pci_irq_deassert(dev); >     } > > > >>   } >> diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c >> index e1a8a88c8c..d936bfca20 100644 >> --- a/hw/pci/pcie_aer.c >> +++ b/hw/pci/pcie_aer.c >> @@ -291,7 +291,9 @@ static void pcie_aer_root_notify(PCIDevice *dev) >>       } else if (msi_enabled(dev)) { >>           msi_notify(dev, pcie_aer_root_get_vector(dev)); >>       } else { >> -        pci_irq_assert(dev); >> +        if (pci_intx(dev) != -1) { >> +            pci_irq_assert(dev); >> +        } > > > And here: > >     if (msix_enabled(dev)) { >         msix_notify(dev, pcie_aer_root_get_vector(dev)); >     } else if (msi_enabled(dev)) { >         msi_notify(dev, pcie_aer_root_get_vector(dev)); >     } else if (pci_intx(dev) != -1) { >         pci_irq_assert(dev); >     } > > > > Thanks, > > > Daniel > >>       } >>   }