From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, Greg Kurz <groug@kaod.org>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v3 00/18] ppc/pnv: add XIVE support for KVM guests
Date: Wed, 18 Sep 2019 10:53:54 +0200 [thread overview]
Message-ID: <5a4efa4c-cdf9-53fe-f49b-ac6146b9b4b6@kaod.org> (raw)
In-Reply-To: <20190918054426.GI2440@umbus.fritz.box>
On 18/09/2019 07:44, David Gibson wrote:
> On Tue, Sep 17, 2019 at 01:54:24PM +0200, Cédric Le Goater wrote:
>> On 31/07/2019 16:12, Cédric Le Goater wrote:
>>> Hello,
>>>
>>> The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
>>> acts as an hypervisor (L0). Supporting emulation of KVM to run guests
>>> (L1) requires a few more extensions, among which guest support for the
>>> XIVE interrupt controller on POWER9 processor.
>>>
>>> The following changes add new per-CPU PowerNV machines and extend the
>>> XIVE models with the new XiveFabric and XivePresenter interfaces to
>>> provide support for XIVE escalations and interrupt resend. This
>>> mechanism is used by XIVE to notify the hypervisor that a vCPU is not
>>> dispatched on a HW thread. Tested on a QEMU PowerNV machine and a
>>> simple QEMU pseries guest doing network on a local bridge.
>>>
>>> The XIVE interrupt controller offers a way to increase the XIVE
>>> resources per chip by configuring multiple XIVE blocks on a chip. This
>>> is not currently supported by the model. However, some configurations,
>>> such as OPAL/skiboot, use one block-per-chip configuration with some
>>> optimizations. One of them is to override the hardwired chip ID by the
>>> block id in the PowerBUS operations and for CAM line compares. This
>>> patchset improves the support for this setup. Tested with 4 chips.
>>
>> David,
>>
>> Do you want me to resend this patchset ? or you just didn't have time
>> to look at it ?
>
> Mostly, I just haven't had time. I'm also finding the patches pretty
> difficult to read and review. I don't think that's an indication
> they're bad, just that what they're doing is necessarily complex, but
> it's still made it hard to tackle them.
I will try to split the initial patches on the presenter a little more.
>> Patch 16 has changed a little since. The get_block_id() handler has
>> moved to the XiveRouterClass.
>
> You, might as well repost, so I'm looking at the latest stuff. I
> can't promise I'll be able to look at the new set terribly soon
> though.
ok.
thanks,
C.
prev parent reply other threads:[~2019-09-18 8:54 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 14:12 [Qemu-devel] [PATCH v3 00/18] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 01/18] ppc/pnv: Introduce PowerNV machines with fixed CPU models Cédric Le Goater
2019-08-05 10:46 ` David Gibson
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 02/18] tests/boot-serial-test: add support for all the PowerNV machines Cédric Le Goater
2019-08-05 12:30 ` David Gibson
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 03/18] ppc/xive: Introduce the XiveFabric and XivePresenter interfaces Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 04/18] ppc/pnv: Implement " Cédric Le Goater
2019-07-31 14:21 ` Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 05/18] ppc/spapr: " Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 06/18] ppc/xive: Use " Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 07/18] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 08/18] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 09/18] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 10/18] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 11/18] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 12/18] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 13/18] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 14/18] ppc/pnv: Skip empty slots of " Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 15/18] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 16/18] ppc/pnv: Extend XivePresenter with a get_block_id() handler Cédric Le Goater
2019-09-02 8:49 ` Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 17/18] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-07-31 14:12 ` [Qemu-devel] [PATCH v3 18/18] ppc/xive: Introduce a xive_os_cam_decode() helper Cédric Le Goater
2019-09-17 11:54 ` [Qemu-devel] [PATCH v3 00/18] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-09-18 5:44 ` David Gibson
2019-09-18 8:53 ` Cédric Le Goater [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5a4efa4c-cdf9-53fe-f49b-ac6146b9b4b6@kaod.org \
--to=clg@kaod.org \
--cc=david@gibson.dropbear.id.au \
--cc=groug@kaod.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).