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From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "alex.williamson@redhat.com" <alex.williamson@redhat.com>,
	"clg@redhat.com" <clg@redhat.com>,
	"eric.auger@redhat.com" <eric.auger@redhat.com>,
	"mst@redhat.com" <mst@redhat.com>,
	"peterx@redhat.com" <peterx@redhat.com>,
	"jasowang@redhat.com" <jasowang@redhat.com>,
	"jgg@nvidia.com" <jgg@nvidia.com>,
	"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
	"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
	"kevin.tian@intel.com" <kevin.tian@intel.com>,
	"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
	"chao.p.peng@intel.com" <chao.p.peng@intel.com>,
	Igor Mammedov <imammedo@redhat.com>,
	Ani Sinha <anisinha@redhat.com>
Subject: Re: [PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR
Date: Wed, 13 Nov 2024 07:16:55 +0000	[thread overview]
Message-ID: <5a65512a-ec4e-4de3-84c9-253a9b7dcba0@eviden.com> (raw)
In-Reply-To: <20241111083457.2090664-18-zhenzhong.duan@intel.com>

Hi Zhenzhong,

Ack

 >cmd


On 11/11/2024 09:34, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
>
>
> Differences:
>
> @@ -1,39 +1,39 @@
>   /*
>    * Intel ACPI Component Architecture
>    * AML/ASL+ Disassembler version 20200925 (64-bit version)
>    * Copyright (c) 2000 - 2020 Intel Corporation
>    *
> - * Disassembly of tests/data/acpi/x86/q35/DMAR.dmar, Mon Nov 11 15:31:18 2024
> + * Disassembly of /tmp/aml-SPJ4W2, Mon Nov 11 15:31:18 2024
>    *
>    * ACPI Data Table [DMAR]
>    *
>    * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
>    */
>
>   [000h 0000   4]                    Signature : "DMAR"    [DMA Remapping table]
>   [004h 0004   4]                 Table Length : 00000078
>   [008h 0008   1]                     Revision : 01
> -[009h 0009   1]                     Checksum : 15
> +[009h 0009   1]                     Checksum : 0C
>   [00Ah 0010   6]                       Oem ID : "BOCHS "
>   [010h 0016   8]                 Oem Table ID : "BXPC    "
>   [018h 0024   4]                 Oem Revision : 00000001
>   [01Ch 0028   4]              Asl Compiler ID : "BXPC"
>   [020h 0032   4]        Asl Compiler Revision : 00000001
>
> -[024h 0036   1]           Host Address Width : 26
> +[024h 0036   1]           Host Address Width : 2F
>   [025h 0037   1]                        Flags : 01
>   [026h 0038  10]                     Reserved : 00 00 00 00 00 00 00 00 00 00
>
>   [030h 0048   2]                Subtable Type : 0000 [Hardware Unit Definition]
>   [032h 0050   2]                       Length : 0040
>
>   [034h 0052   1]                        Flags : 00
>   [035h 0053   1]                     Reserved : 00
>   [036h 0054   2]           PCI Segment Number : 0000
>   [038h 0056   8]        Register Base Address : 00000000FED90000
>
>   [040h 0064   1]            Device Scope Type : 03 [IOAPIC Device]
>   [041h 0065   1]                 Entry Length : 08
>   [042h 0066   2]                     Reserved : 0000
>   [044h 0068   1]               Enumeration ID : 00
>   [045h 0069   1]               PCI Bus Number : FF
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
>   tests/qtest/bios-tables-test-allowed-diff.h |   1 -
>   tests/data/acpi/x86/q35/DMAR.dmar           | Bin 120 -> 120 bytes
>   2 files changed, 1 deletion(-)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
> index 46f80be9ca..dfb8523c8b 100644
> --- a/tests/qtest/bios-tables-test-allowed-diff.h
> +++ b/tests/qtest/bios-tables-test-allowed-diff.h
> @@ -1,2 +1 @@
>   /* List of comma-separated changed AML files to ignore */
> -"tests/data/acpi/x86/q35/DMAR.dmar",
> diff --git a/tests/data/acpi/x86/q35/DMAR.dmar b/tests/data/acpi/x86/q35/DMAR.dmar
> index 0dca6e68ad8a8ca5b981bcfbc745385a63e9f216..0c05976715c6f2f6ec46ef6d37790f86a392b5ea 100644
> GIT binary patch
> delta 21
> ccmb=Z;BxVG460yYU|{5#$R)+7KT$Op05(qqk^lez
>
> delta 21
> ccmb=Z;BxVG460yYU|<xT$R)+7Hc>Sg05*ICk^lez
>
> --
> 2.34.1
>

  reply	other threads:[~2024-11-13  7:18 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-11  8:34 [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 01/20] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 02/20] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 03/20] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 05/20] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 06/20] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 07/20] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 08/20] intel_iommu: Check stage-1 translation result with interrupt range Zhenzhong Duan
2024-11-13  6:55   ` CLEMENT MATHIEU--DRIF
2024-11-13  8:49     ` Duan, Zhenzhong
2024-11-14  6:04       ` CLEMENT MATHIEU--DRIF
2024-12-04  2:11   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 11/20] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 12/20] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-12-04  3:27   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 14/20] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 15/20] tests/acpi: q35: allow DMAR acpi table changes Zhenzhong Duan
2024-11-20  6:09   ` CLEMENT MATHIEU--DRIF
2024-12-04  3:27   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Zhenzhong Duan
2024-12-04  3:28   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR Zhenzhong Duan
2024-11-13  7:16   ` CLEMENT MATHIEU--DRIF [this message]
2024-11-13  8:50     ` Duan, Zhenzhong
2024-11-11  8:34 ` [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode Zhenzhong Duan
2024-11-19  6:54   ` CLEMENT MATHIEU--DRIF
2024-11-19  7:28     ` Duan, Zhenzhong
2024-11-19  8:59       ` CLEMENT MATHIEU--DRIF
2024-11-19  9:25         ` Duan, Zhenzhong
2024-11-20  6:11           ` CLEMENT MATHIEU--DRIF
2024-12-04  3:34   ` Jason Wang
2024-12-04  6:14     ` CLEMENT MATHIEU--DRIF
2024-12-09  3:13       ` Jason Wang
2024-12-09  6:14         ` CLEMENT MATHIEU--DRIF
2024-12-09  6:24           ` Jason Wang
2024-12-09  6:42             ` CLEMENT MATHIEU--DRIF
2024-12-11  2:22               ` Duan, Zhenzhong
2024-12-11  3:03                 ` Jason Wang
2024-12-11  6:08                   ` CLEMENT MATHIEU--DRIF
2024-11-11  8:34 ` [PATCH v5 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 20/20] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-12-03  9:00 ` [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Duan, Zhenzhong

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