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([2602:47:d49d:ec01:5aa4:aba1:1c91:a9b7]) by smtp.gmail.com with ESMTPSA id bb2-20020a170902bc8200b001822121c45asm2659438plb.28.2022.10.10.07.02.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Oct 2022 07:02:20 -0700 (PDT) Message-ID: <5a67553b-18ab-a70d-95b5-b8b858b888c0@linaro.org> Date: Mon, 10 Oct 2022 07:02:18 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH] include/qemu/atomic128: Support 16-byte atomic read/write for Intel AVX To: Peter Maydell Cc: qemu-devel@nongnu.org, pbonzini@redhat.com References: <20221008153646.1504760-1-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.007, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/10/22 02:49, Peter Maydell wrote: > On Sat, 8 Oct 2022 at 16:38, Richard Henderson > wrote: >> >> Intel has now given guarantees about the atomicity of SSE read >> and write instructions on cpus supporting AVX. We can use these >> instead of the much slower cmpxchg16b. >> >> Derived from https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 >> >> Signed-off-by: Richard Henderson > >> + /* >> + * The xgetbv instruction is not available to older versions of >> + * the assembler, so we encode the instruction manually. >> + */ >> + asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (0)); > > This would make the third place in the tree where we hand-code > this asm instruction (we already do it in the xgetbv() function > in target/i386/hvf/x86_cpuid.c and opencoded in tcg_target_init()): > can we abstract this out somehow, please? > > (There is also a just-written-out "xgetbv" in init_cpuid_cache(), > but that one's guarded by ifdefs so presumably OK.) It's also possible that the Xcode revision that didn't know xgetbv is now unsupported. Something to check, I suppose. r~