From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Tao Tang <tangtao1634@phytium.com.cn>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Eric Auger <eric.auger@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>,
Chen Baozi <chenbaozi@phytium.com.cn>
Subject: Re: [RFC 01/11] hw/arm/smmuv3: Introduce secure registers and commands
Date: Mon, 11 Aug 2025 12:22:49 +0200 [thread overview]
Message-ID: <5a955f10-88bc-4590-9887-ec0f95af3e17@linaro.org> (raw)
In-Reply-To: <20250806151134.365755-2-tangtao1634@phytium.com.cn>
Hi,
On 6/8/25 17:11, Tao Tang wrote:
> The Arm SMMUv3 architecture defines a set of registers and commands for
> managing secure transactions and context.
>
> This patch introduces the definitions for these secure registers and
> commands within the SMMUv3 device model internal header.
>
> Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
> ---
> hw/arm/smmuv3-internal.h | 57 ++++++++++++++++++++++++++++++++++++++++
> include/hw/arm/smmuv3.h | 23 ++++++++++++++++
> 2 files changed, 80 insertions(+)
> diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
> index d183a62766..72ad042514 100644
> --- a/include/hw/arm/smmuv3.h
> +++ b/include/hw/arm/smmuv3.h
> @@ -63,6 +63,29 @@ struct SMMUv3State {
> qemu_irq irq[4];
> QemuMutex mutex;
> char *stage;
> +
> + /* Secure state */
> + uint32_t secure_idr[5];
> + uint32_t secure_cr[3];
> + uint32_t secure_cr0ack;
> + uint32_t secure_init;
> + uint32_t secure_gbpa;
> + uint32_t secure_irq_ctrl;
> + uint32_t secure_gerror;
> + uint32_t secure_gerrorn;
> + uint64_t secure_gerror_irq_cfg0;
> + uint32_t secure_gerror_irq_cfg1;
> + uint32_t secure_gerror_irq_cfg2;
> + uint64_t secure_strtab_base;
> + uint32_t secure_strtab_base_cfg;
> + uint8_t secure_sid_split;
> + uint32_t secure_features;
> +
> + uint64_t secure_eventq_irq_cfg0;
> + uint32_t secure_eventq_irq_cfg1;
> + uint32_t secure_eventq_irq_cfg2;
> +
> + SMMUQueue secure_eventq, secure_cmdq;
Note, we could also add these fields as
struct {
uint32_t idr[5];
...
} secure;
With some IDEs it allows to only expand which set you are
interested in when debugging.
I then since it is mostly the same banked set, I wonder why we
don't extract the state and bank it:
struct {
uint32_t idr[5];
...
} state[REG_NUM_BANKS];
I haven't looked at the rest, but this might simplify the
implementation.
Then maybe we can use the ARMASIdx enum as index.
> };Shouldn't we add a subsection for these new fields in vmstate_smmuv3?
(If using banked state, then this is greatly simplified IMHO).
Regards,
Phil.
next prev parent reply other threads:[~2025-08-11 10:24 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-06 15:11 [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State Tao Tang
2025-08-06 15:11 ` [RFC 01/11] hw/arm/smmuv3: Introduce secure registers and commands Tao Tang
2025-08-11 10:22 ` Philippe Mathieu-Daudé [this message]
2025-08-11 10:43 ` Philippe Mathieu-Daudé
2025-08-18 21:21 ` Mostafa Saleh
2025-08-06 15:11 ` [RFC 02/11] hw/arm/smmuv3: Implement read/write logic for secure registers Tao Tang
2025-08-06 21:53 ` Pierrick Bouvier
2025-08-10 16:54 ` Tao Tang
2025-08-12 17:12 ` Pierrick Bouvier
2025-08-18 21:24 ` Mostafa Saleh
2025-08-20 15:21 ` Tao Tang
2025-08-23 10:41 ` Mostafa Saleh
2025-09-11 15:27 ` Tao Tang
2025-09-15 9:14 ` Mostafa Saleh
2025-09-15 9:34 ` Eric Auger
2025-08-06 15:11 ` [RFC 03/11] hw/arm/smmuv3: Implement S_INIT for secure initialization Tao Tang
2025-08-18 21:26 ` Mostafa Saleh
2025-08-20 16:01 ` Tao Tang
2025-08-06 15:11 ` [RFC 04/11] hw/arm/smmuv3: Enable command processing for the Secure state Tao Tang
2025-08-06 21:55 ` Pierrick Bouvier
2025-08-10 16:59 ` Tao Tang
2025-08-11 10:34 ` Philippe Mathieu-Daudé
2025-08-12 17:27 ` Pierrick Bouvier
2025-08-12 17:39 ` Philippe Mathieu-Daudé
2025-08-12 18:42 ` Peter Maydell
2025-08-15 6:02 ` Tao Tang
2025-08-15 14:53 ` Peter Maydell
2025-08-17 3:46 ` Tao Tang
2025-08-06 15:11 ` [RFC 05/11] hw/arm/smmuv3: Support secure event queue and error handling Tao Tang
2025-08-11 10:41 ` Philippe Mathieu-Daudé
2025-08-06 15:11 ` [RFC 06/11] hw/arm/smmuv3: Plumb security state through core functions Tao Tang
2025-08-18 21:28 ` Mostafa Saleh
2025-08-20 16:25 ` Tao Tang
2025-08-23 10:43 ` Mostafa Saleh
2025-08-06 15:11 ` [RFC 07/11] hw/arm/smmuv3: Add separate address space for secure SMMU accesses Tao Tang
2025-08-06 15:11 ` [RFC 08/11] hw/arm/smmuv3: Enable secure-side stage 2 TLB invalidations Tao Tang
2025-08-06 15:11 ` [RFC 09/11] hw/arm/smmuv3: Make the configuration cache security-state aware Tao Tang
2025-08-06 15:11 ` [RFC 10/11] hw/arm/smmuv3: Differentiate secure TLB entries via keying Tao Tang
2025-08-06 21:11 ` [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State Pierrick Bouvier
2025-08-06 21:28 ` Pierrick Bouvier
2025-08-10 16:11 ` Tao Tang
2025-08-11 10:26 ` Philippe Mathieu-Daudé
2025-08-12 17:50 ` Pierrick Bouvier
2025-08-12 18:04 ` Pierrick Bouvier
2025-08-15 5:49 ` Tao Tang
2025-09-30 4:04 ` Tao Tang
2025-08-18 21:52 ` Mostafa Saleh
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