Re: [PATCH v3 2/4] target/arm: Add support for FEAT_DIT, Data Independent Timing

[Richard Henderson <richard.henderson@linaro.org>]

On 1/27/21 6:45 PM, Rebecca Cran wrote:
> Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
> feature for ARMv8.4. Since virtual machine execution is largely
> nondeterministic and TCG is outside of the security domain, it's
> implemented as a NOP.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


This misses the convert from AA32 CPSR to AA64 SPSR on exception entry (and
vice-versa on return).

In particular: CPSR.DIT (bit 21) -> SPSR_EL1.DIT (bit 24), and merging
PSTATE.SS into SPSR_EL1.SS (bit 21).


r~

> ---
>  target/arm/cpu.h           | 12 +++++++++++
>  target/arm/helper.c        | 22 ++++++++++++++++++++
>  target/arm/internals.h     |  6 ++++++
>  target/arm/translate-a64.c | 12 +++++++++++
>  4 files changed, 52 insertions(+)
> 
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index df0d6778330f..56b1053dfdec 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1242,6 +1242,7 @@ void pmu_init(ARMCPU *cpu);
>  #define CPSR_IT_2_7 (0xfc00U)
>  #define CPSR_GE (0xfU << 16)
>  #define CPSR_IL (1U << 20)
> +#define CPSR_DIT (1U << 21)
>  #define CPSR_PAN (1U << 22)
>  #define CPSR_J (1U << 24)
>  #define CPSR_IT_0_1 (3U << 25)
> @@ -1309,6 +1310,7 @@ void pmu_init(ARMCPU *cpu);
>  #define PSTATE_SS (1U << 21)
>  #define PSTATE_PAN (1U << 22)
>  #define PSTATE_UAO (1U << 23)
> +#define PSTATE_DIT (1U << 24)
>  #define PSTATE_TCO (1U << 25)
>  #define PSTATE_V (1U << 28)
>  #define PSTATE_C (1U << 29)
> @@ -3875,6 +3877,11 @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
>      return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
>  }
>  
> +static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
> +{
> +    return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
> +}
> +
>  /*
>   * 64-bit feature tests via id registers.
>   */
> @@ -4119,6 +4126,11 @@ static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
>      return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
>  }
>  
> +static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
> +{
> +    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
> +}
> +
>  /*
>   * Feature tests for "does this exist in either 32-bit or 64-bit?"
>   */
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 7b7e72ba878c..435208121e9f 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4419,6 +4419,24 @@ static const ARMCPRegInfo uao_reginfo = {
>      .readfn = aa64_uao_read, .writefn = aa64_uao_write
>  };
>  
> +static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> +    return env->pstate & PSTATE_DIT;
> +}
> +
> +static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri,
> +                           uint64_t value)
> +{
> +    env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT);
> +}
> +
> +static const ARMCPRegInfo dit_reginfo = {
> +    .name = "DIT", .state = ARM_CP_STATE_AA64,
> +    .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5,
> +    .type = ARM_CP_NO_RAW, .access = PL0_RW,
> +    .readfn = aa64_dit_read, .writefn = aa64_dit_write
> +};
> +
>  static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
>                                                const ARMCPRegInfo *ri,
>                                                bool isread)
> @@ -8203,6 +8221,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>          define_one_arm_cp_reg(cpu, &uao_reginfo);
>      }
>  
> +    if (cpu_isar_feature(aa64_dit, cpu)) {
> +        define_one_arm_cp_reg(cpu, &dit_reginfo);
> +    }
> +
>      if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
>          define_arm_cp_regs(cpu, vhe_reginfo);
>      }
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 853fa88fd616..3d11e42d8e1b 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1222,6 +1222,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
>      if (isar_feature_aa32_pan(id)) {
>          valid |= CPSR_PAN;
>      }
> +    if (isar_feature_aa32_dit(id)) {
> +        valid |= CPSR_DIT;
> +    }
>  
>      return valid;
>  }
> @@ -1240,6 +1243,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
>      if (isar_feature_aa64_uao(id)) {
>          valid |= PSTATE_UAO;
>      }
> +    if (isar_feature_aa64_dit(id)) {
> +        valid |= PSTATE_DIT;
> +    }
>      if (isar_feature_aa64_mte(id)) {
>          valid |= PSTATE_TCO;
>      }
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index ffc060e5d70c..1c4b8d02f3b8 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -1700,6 +1700,18 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
>          tcg_temp_free_i32(t1);
>          break;
>  
> +    case 0x1a: /* DIT */
> +        if (!dc_isar_feature(aa64_dit, s)) {
> +            goto do_unallocated;
> +        }
> +        if (crm & 1) {
> +            set_pstate_bits(PSTATE_DIT);
> +        } else {
> +            clear_pstate_bits(PSTATE_DIT);
> +        }
> +        /* There's no need to rebuild hflags because DIT is a nop */
> +        break;
> +
>      case 0x1e: /* DAIFSet */
>          t1 = tcg_const_i32(crm);
>          gen_helper_msr_i_daifset(cpu_env, t1);
>