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From: David Hildenbrand <david@redhat.com>
To: Ani Sinha <anisinha@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Xiao Guangrong" <xiaoguangrong.eric@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [PATCH] mem/x86: add processor address space check for VM memory
Date: Mon, 18 Sep 2023 12:19:35 +0200	[thread overview]
Message-ID: <5b22fff5-270f-0ab5-1ee5-2e54f491aefd@redhat.com> (raw)
In-Reply-To: <CAK3XEhMTSP7TkJgKX1_VxUVxaoU1jX8d_i-0H4t=bNktY5wo5g@mail.gmail.com>

On 18.09.23 12:11, Ani Sinha wrote:

> 
>     Ok hopefully my last question. I am still confused on something.
>     Does the above mean that the hole64 will actually start from an
>     address that is beyond maxram? Like basically if you added all of
>     ram_below_4G, ram_above_4G, hot plug_mem and pci_hole64 then can it
>     exceed maxram? I think it will. Does this not an issue?

If you'd have a 2 GiB VM, the device memory region and hole64 would 
always be placed >= 4 GiB address, yes.

As maxram is just a size, and not a PFN, I don't think there is any 
issue with that.

ms->maxram_size is usually only used in combination with ms->ram_size to
detect if memory devices will be enabled, and to size that region for 
memory devices.

-- 
Cheers,

David / dhildenb



  parent reply	other threads:[~2023-09-18 10:20 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-08  9:50 [PATCH] mem/x86: add processor address space check for VM memory Ani Sinha
2023-09-08 10:28 ` David Hildenbrand
2023-09-08 14:12   ` Ani Sinha
2023-09-08 14:16     ` David Hildenbrand
2023-09-08 15:13       ` Ani Sinha
2023-09-08 16:02         ` David Hildenbrand
2023-09-08 16:04           ` David Hildenbrand
2023-09-12 10:41           ` Ani Sinha
2023-09-12 15:34             ` David Hildenbrand
2023-09-14  5:53               ` Ani Sinha
2023-09-14  8:37                 ` David Hildenbrand
2023-09-14 11:21                   ` Ani Sinha
2023-09-14 11:49                     ` David Hildenbrand
2023-09-15 10:38                       ` Ani Sinha
2023-09-18  9:33                         ` David Hildenbrand
2023-09-18 10:07                           ` Ani Sinha
2023-09-18 10:09                             ` David Hildenbrand
2023-09-18 10:11                               ` Ani Sinha
2023-09-18 10:14                                 ` Ani Sinha
2023-09-18 10:19                                 ` David Hildenbrand [this message]
2023-09-18 10:54                                   ` Ani Sinha
2023-09-18 10:58                                     ` David Hildenbrand
2023-09-18 11:00                                       ` Ani Sinha
2023-09-18 11:02                                         ` Ani Sinha
2023-09-18 11:02                                         ` David Hildenbrand
2023-09-18 11:04                                           ` Ani Sinha
2023-09-14 17:11                   ` Ani Sinha
2023-09-16  5:17                   ` Ani Sinha
2023-09-08 16:04         ` Philippe Mathieu-Daudé

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