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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id n7-20020a6543c7000000b00502f9fba637sm4206545pgp.68.2023.02.27.10.40.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 10:40:53 -0800 (PST) Message-ID: <5b3120cd-ddfb-770b-3216-0f02e89c9c24@linaro.org> Date: Mon, 27 Feb 2023 08:40:50 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [RFC PATCH 10/43] target/loongarch: Implement vaddw/vsubw Content-Language: en-US To: gaosong , qemu-devel@nongnu.org References: <20221224081633.4185445-1-gaosong@loongson.cn> <20221224081633.4185445-11-gaosong@loongson.cn> <268ef762-fce5-ca47-d5f7-bd60955a3a0f@linaro.org> <1ad204fc-8f7e-0f1c-e8f6-163d11f3880b@linaro.org> <5ce46e81-b2c3-8b45-1bd9-9705520f4557@loongson.cn> From: Richard Henderson In-Reply-To: <5ce46e81-b2c3-8b45-1bd9-9705520f4557@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/27/23 02:55, gaosong wrote: > > 在 2023/2/25 上午3:24, Richard Henderson 写道: >>>          { >>>              .fniv = gen_vaddwev_s, >>>              .fno = gen_helper_vaddwev_q_d, >>>              .opt_opc = vecop_list, >>>              .vece = MO_128 >>>          }, >> >> There are no 128-bit vector operations; you'll need to do this one differently. >> >> Presumably just load the two 64-bit elements, sign-extend into 128-bits, add with >> tcg_gen_add2_i64, and store the two 64-bit elements as output.  But that won't fit into >> the tcg_gen_gvec_3 interface. >> > 'sign-extend into 128-bits,'   Could you give a example? Well, for vadd, as the example we have been using: tcg_gen_ld_i64(lo1, cpu_env, offsetof(vector_reg[A].lo)); tcg_gen_ld_i64(lo2, cpu_env, offsetof(vector_reg[B].lo)); tcg_gen_sari_i64(hi1, lo1, 63); tcg_gen_sari_i64(hi2, lo2, 63); tcg_gen_add2_i64(lo1, hi1, lo1, hi1, lo2, hi2); tcg_gen_st_i64(lo1, cpu_env, offsetof(vector_reg[R].lo)); tcg_gen_st_i64(hi1, cpu_env, offsetof(vector_reg[R].hi)); The middle two sari operations replicate the sign bit across the entire high word, so the pair of variables constitute a sign-extended 128-bit value. > I see a example at target/ppc/translate/vmx-impl.c.inc >     static bool do_vx_vprtyb(DisasContext *ctx, arg_VX_tb *a, unsigned vece) >     { >             ... >             { >             .fno = gen_helper_VPRTYBQ, >             .vece = MO_128 >             }, >             tcg_gen_gvec_2(avr_full_offset(a->vrt), avr_full_offset(a->vrb), >                                16, 16, &op[vece - MO_32]); >         return true; >     } > TRANS(VPRTYBQ, do_vx_vprtyb, MO_128) > ... > > do_vx_vprtyb  fit the fno into the tcg_gen_gvec_2. > I am not sure this  example is right. Ah, well. When .fno is the only callback, the implementation is entirely out-of-line, and the .vece member is not used. I see that is confusing. r~