From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IU5xy-00033T-LM for qemu-devel@nongnu.org; Sat, 08 Sep 2007 15:27:38 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IU5xx-00032r-OP for qemu-devel@nongnu.org; Sat, 08 Sep 2007 15:27:38 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IU5xx-00032h-KF for qemu-devel@nongnu.org; Sat, 08 Sep 2007 15:27:37 -0400 Received: from fk-out-0910.google.com ([209.85.128.189]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IU5xx-0001xu-2u for qemu-devel@nongnu.org; Sat, 08 Sep 2007 15:27:37 -0400 Received: by fk-out-0910.google.com with SMTP id 19so1393069fkr for ; Sat, 08 Sep 2007 12:27:36 -0700 (PDT) Message-ID: <5b31733c0709081227w3e5f1036odbc649edfdc8c79b@mail.gmail.com> Date: Sat, 8 Sep 2007 21:27:35 +0200 From: "Filip Navara" Sender: filip.navara@gmail.com MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_4452_12350031.1189279655906" Subject: [Qemu-devel] [PATCH] Intel cache info Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org ------=_Part_4452_12350031.1189279655906 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Fix the CPUID function 2 to correctly report cache info for the particular processor. I chose the values closest to the ones reported in the AMD registers. This is important for operating systems that detect cache line width and later call CLFLUSH for each line. In the previous implementation the values didn't specify L2 cache line width and so Darwin endlessly looped trying to flush them. ------=_Part_4452_12350031.1189279655906 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Fix the CPUID function 2 to correctly report cache info for the particular processor. I chose the values closest to the ones reported in the AMD registers. This is important for operating systems that detect cache line width and later call CLFLUSH for each line. In the previous implementation the values didn't specify L2 cache line width and so Darwin endlessly looped trying to flush them.
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