Re: [Qemu-devel] [PATCH] Intel cache info

["Filip Navara" <xnavara@volny.cz>]

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Here it is, sorry for the delay.

Best regards,
Filip Navara

On 9/9/07, Thiemo Seufer <ths@networkno.de> wrote:
>
> Filip Navara wrote:
> > Fix the CPUID function 2 to correctly report cache info for the
> particular
> > processor. I chose the values closest to the ones reported in the AMD
> > registers. This is important for operating systems that detect cache
> line
> > width and later call CLFLUSH for each line. In the previous
> implementation
> > the values didn't specify L2 cache line width and so Darwin endlessly
> looped
> > trying to flush them.
>
> No patch attached.
>
>
> Thiemo
>

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Index: target-i386/helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-i386/helper.c,v
retrieving revision 1.84
diff -u -r1.84 helper.c
--- target-i386/helper.c	26 Jun 2007 08:35:18 -0000	1.84
+++ target-i386/helper.c	8 Sep 2007 16:07:23 -0000
@@ -1657,10 +1657,10 @@
         break;
     case 2:
         /* cache info: needed for Pentium Pro compatibility */
-        EAX = 0x410601;
+        EAX = 1;
         EBX = 0;
         ECX = 0;
-        EDX = 0;
+        EDX = 0x2c307d; 
         break;
     case 0x80000000:
         EAX = env->cpuid_xlevel;