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Date: Tue, 11 Sep 2007 09:20:04 +0200
From: "Filip Navara" <xnavara@volny.cz>
Sender: filip.navara@gmail.com
Subject: Re: [Qemu-devel] [PATCH] Intel cache info
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To: Thiemo Seufer <ths@networkno.de>
Cc: qemu-devel@nongnu.org

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Here it is, sorry for the delay.

Best regards,
Filip Navara

On 9/9/07, Thiemo Seufer <ths@networkno.de> wrote:
>
> Filip Navara wrote:
> > Fix the CPUID function 2 to correctly report cache info for the
> particular
> > processor. I chose the values closest to the ones reported in the AMD
> > registers. This is important for operating systems that detect cache
> line
> > width and later call CLFLUSH for each line. In the previous
> implementation
> > the values didn't specify L2 cache line width and so Darwin endlessly
> looped
> > trying to flush them.
>
> No patch attached.
>
>
> Thiemo
>

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Here it is, sorry for the delay.<br><br>Best regards,<br>Filip Navara<br><br><div><span class="gmail_quote">On 9/9/07, <b class="gmail_sendername">Thiemo Seufer</b> &lt;<a href="mailto:ths@networkno.de">ths@networkno.de</a>
&gt; wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">Filip Navara wrote:<br>&gt; Fix the CPUID function 2 to correctly report cache info for the particular
<br>&gt; processor. I chose the values closest to the ones reported in the AMD<br>&gt; registers. This is important for operating systems that detect cache line<br>&gt; width and later call CLFLUSH for each line. In the previous implementation
<br>&gt; the values didn&#39;t specify L2 cache line width and so Darwin endlessly looped<br>&gt; trying to flush them.<br><br>No patch attached.<br><br><br>Thiemo<br></blockquote></div><br>

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