From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MGgUn-00068T-Tq for qemu-devel@nongnu.org; Tue, 16 Jun 2009 17:47:09 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MGgUi-00065R-5l for qemu-devel@nongnu.org; Tue, 16 Jun 2009 17:47:09 -0400 Received: from [199.232.76.173] (port=36390 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MGgUi-00065K-19 for qemu-devel@nongnu.org; Tue, 16 Jun 2009 17:47:04 -0400 Received: from mail-ew0-f220.google.com ([209.85.219.220]:56172) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MGgUh-0007ds-Fn for qemu-devel@nongnu.org; Tue, 16 Jun 2009 17:47:03 -0400 Received: by ewy20 with SMTP id 20so513540ewy.34 for ; Tue, 16 Jun 2009 14:47:02 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <5b31733c0906161349l62255380rbd63647e7d9ee415@mail.gmail.com> References: <200707021527.54435.uli@suse.de> <200707031645.51832.uli@suse.de> <5b31733c0906151211o1c95245ay38f2d09c123ea0c9@mail.gmail.com> <200906161825.18981.paul@codesourcery.com> <20090616190214.GM11893@shareable.org> <5b31733c0906161349l62255380rbd63647e7d9ee415@mail.gmail.com> Date: Tue, 16 Jun 2009 23:47:01 +0200 Message-ID: <5b31733c0906161447q5bdb6f1bq3d7d3b07977df7be@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH] ARM7TDMI emulation From: Filip Navara Content-Type: multipart/alternative; boundary=00504502d2f667527f046c7e1d71 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jamie Lokier Cc: Paul Brook , qemu-devel@nongnu.org --00504502d2f667527f046c7e1d71 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit On Tue, Jun 16, 2009 at 10:49 PM, Filip Navara wrote: > Do you know of a good summary reference which lists which instructions >> are available in each ARM architecture level from ARMv4 up to ARMv7 >> and it's variants? >> > > My main reference are the technical reference manuals for ARM processors > downloaded from Atmel site. I'm not sure about the license, but it states > "This document is Open Access. This document has no restriction on > distribution." Other reference sources are Skyeye emulation (has to be taken > with grain of salt and checked against the manuals, but it makes distinction > between v4, v5 and v5e) and Paul Brook. > > I've certainly missed handling BLX (at least on three places) in the patch > and possibly more. I'll post an updated patch soon. > The list may not be complete, but this is what I compiled from various sources, including ARM official documentation. For the ARMv4t emulation I'd need to do the following: - Treat CDP2, LDC2, STC2, BLX, MRC2, MCR2, MCRR, SMUL, SMLA, SMULW, SMLAW, SMLAL, QADD, QSUB, QDADD, QDSUB, BKPT, 64-bit LDR/STR, PLD as undefined instructions. - Do not change to/from Thumb mode on LDR/LDM/POP to r15 depending on the bit 0 of the value. - Add the base updated data-abort model. Other changes between ARMv5 and ARMv4 include: - MULS, MLAS corrupt C flag - UMULLS, UMLALS, SMULLS and SMLALS corrupt the C and V flags I don't plan to implement corrupting the flags. Implementing ARMv4 instead of ARMv4t would then be matter of disabling the BX instruction. Anything I missed? Best regards, Filip Navara --00504502d2f667527f046c7e1d71 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
On Tue, Jun 16, 2009 at 10:49 PM, Filip Navara <= span dir=3D"ltr"><filip.navara= @gmail.com> wrote:
Do you know of a good summary reference which lists which instru= ctions
are available in each ARM architecture level from ARMv4 up to ARMv7
and it's variants?

My main referen= ce are the technical reference manuals for ARM processors downloaded from A= tmel site. I'm not sure about the license, but it states "This doc= ument is Open Access. This document has no restriction on distribution.&quo= t; Other reference sources are Skyeye emulation (has to be taken with grain= of salt and checked against the manuals, but it makes distinction between = v4, v5 and v5e) and Paul Brook.

I've certainly missed handling BLX (at least on thr= ee places) in the patch and possibly more. I'll post an updated patch s= oon.

The list may not be complete, bu= t this is what I compiled from various sources, including ARM official docu= mentation. For the ARMv4t emulation I'd need to do the following:

- Treat=A0CDP2, LDC2, STC2, BLX, MRC2, MCR2, MCRR,=A0SM= UL, SMLA, SMULW, SMLAW,=A0SMLAL,=A0QADD, QSUB, QDADD, QDSUB, BKPT, 64-bit L= DR/STR, PLD as undefined instructions.
- Do not change to/fr= om Thumb mode on LDR/LDM/POP to r15 depending on the bit 0 of the value.
- Add the base updated data-abort model.

Othe= r changes between ARMv5 and ARMv4 include:

- = MULS, MLAS corrupt C flag
- UMULLS, UMLALS, SMULLS and SMLALS cor= rupt the C and V flags

I don't plan to implement corrupting the flag= s. Implementing ARMv4 instead of ARMv4t would then be matter of disabling t= he BX instruction. Anything I missed?

Best regards= ,
Filip Navara


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