OT: TCG SSA, speed, misc (was Re: [Qemu-devel] Re: [PATCH 08/11] QMP: Port balloon command)

[Filip Navara <filip.navara@gmail.com>]

On Sun, Jun 28, 2009 at 7:51 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
> On 6/28/09, Filip Navara <filip.navara@gmail.com> wrote:
>> On Sun, Jun 28, 2009 at 5:52 PM, Avi Kivity<avi@redhat.com> wrote:
>>  > It really isn't very complicated, and
>>  > the thread only got so long because the topic is relatively simple.  Post an
>>  > RFC and a mile-long patchset about changing TCG to SSA form, and see how you
>>  > get no replies.
>>
>>
>> I wouldn't even dare to push the SSA patch... Mile-long doesn't
>>  describe it precisely enough. Imagine it was applied to all the
>>  targets.

Just to be perfectly clear, this was meant as a joke. I don't have any
working SSA patch and neither am I working on one right now, but I am
interested in the topic. Main reason for my interest is this:

http://www.info.uni-karlsruhe.de/lehre/2006SS/uebau2/folien/08-RA_v1_4.pdf
http://www.info.uni-karlsruhe.de/~hack/ra_ssa.pdf

I'd like to know if the register allocation can be improved. I don't
believe SSA would help much in anything else since the input code to
translators was already compiled with optimizing compiler and so most
of the SSA-based optimizations would be redundant.

Doing a profiling run on several ARM demo programs showed that most of
the generated code was doing load/store operations to the machine
registers (in CPU_env). Sample run of FreeRTOS looked like this (OP
counts):

movi_i32 1603
ld_i32 1305
st_i32 1174
add_i32 530
...

If there could be done something that would allow the guest registers
to be stored in host registers, even if for a temporary amount of time
it would certainly help the guests that I'm dealing with.

Best regards,
Filip Navara