From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MKyyv-0007QG-2c for qemu-devel@nongnu.org; Sun, 28 Jun 2009 14:20:01 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MKyyq-0007O5-GQ for qemu-devel@nongnu.org; Sun, 28 Jun 2009 14:20:00 -0400 Received: from [199.232.76.173] (port=46294 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MKyyq-0007Nw-AW for qemu-devel@nongnu.org; Sun, 28 Jun 2009 14:19:56 -0400 Received: from mail-ew0-f211.google.com ([209.85.219.211]:43145) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MKyyq-0001yO-4d for qemu-devel@nongnu.org; Sun, 28 Jun 2009 14:19:56 -0400 Received: by ewy7 with SMTP id 7so4271902ewy.34 for ; Sun, 28 Jun 2009 11:19:54 -0700 (PDT) MIME-Version: 1.0 Date: Sun, 28 Jun 2009 20:19:54 +0200 Message-ID: <5b31733c0906281119r7ea485b6k81f8e59fd3aa4926@mail.gmail.com> Subject: OT: TCG SSA, speed, misc (was Re: [Qemu-devel] Re: [PATCH 08/11] QMP: Port balloon command) From: Filip Navara Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Anthony Liguori , ehabkost@redhat.com, jan.kiszka@siemens.com, dlaor@redhat.com, qemu-devel@nongnu.org, Luiz Capitulino , Avi Kivity On Sun, Jun 28, 2009 at 7:51 PM, Blue Swirl wrote: > On 6/28/09, Filip Navara wrote: >> On Sun, Jun 28, 2009 at 5:52 PM, Avi Kivity wrote: >> =A0> It really isn't very complicated, and >> =A0> the thread only got so long because the topic is relatively simple.= =A0Post an >> =A0> RFC and a mile-long patchset about changing TCG to SSA form, and se= e how you >> =A0> get no replies. >> >> >> I wouldn't even dare to push the SSA patch... Mile-long doesn't >> =A0describe it precisely enough. Imagine it was applied to all the >> =A0targets. Just to be perfectly clear, this was meant as a joke. I don't have any working SSA patch and neither am I working on one right now, but I am interested in the topic. Main reason for my interest is this: http://www.info.uni-karlsruhe.de/lehre/2006SS/uebau2/folien/08-RA_v1_4.pdf http://www.info.uni-karlsruhe.de/~hack/ra_ssa.pdf I'd like to know if the register allocation can be improved. I don't believe SSA would help much in anything else since the input code to translators was already compiled with optimizing compiler and so most of the SSA-based optimizations would be redundant. Doing a profiling run on several ARM demo programs showed that most of the generated code was doing load/store operations to the machine registers (in CPU_env). Sample run of FreeRTOS looked like this (OP counts): movi_i32 1603 ld_i32 1305 st_i32 1174 add_i32 530 ... If there could be done something that would allow the guest registers to be stored in host registers, even if for a temporary amount of time it would certainly help the guests that I'm dealing with. Best regards, Filip Navara