qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	David Gibson <david@gibson.dropbear.id.au>
Cc: lvivier@redhat.com, "Cédric Le Goater" <clg@kaod.org>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org, groug@kaod.org
Subject: Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
Date: Fri, 01 Apr 2022 12:59:30 +1100	[thread overview]
Message-ID: <5b581691e0063d831649b4a6e36f07ef00e42861.camel@kernel.crashing.org> (raw)
In-Reply-To: <CAFEAcA-_KiR1ZVPu3auXkTE3CtayyfPwT+0sd2y+X_5xOdGk_w@mail.gmail.com>

On Thu, 2022-03-31 at 18:51 +0100, Peter Maydell wrote:
> 
> Hi; Coverity has just spotted an error in this old change
> (CID 1487176):

Oh my this is old ... I don't work for IBM anymore but I found the
relevant doc here: 
https://wiki.raptorcs.com/w/images/a/a5/POWER9_PCIe_controller_v11_27JUL2018_pub.pdf

So....

> > +++ b/hw/pci-host/pnv_phb4_pec.c
> > +static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr,
> > +                                    uint64_t val, unsigned size)
> > +{
> > +    PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
> > +    uint32_t reg = addr >> 3;
> > +
> > +    switch (reg) {
> > +    case PEC_PCI_PBAIB_HW_CONFIG:
> > +    case PEC_PCI_PBAIB_READ_STK_OVR:
> > +        pec->pci_regs[reg] = val;
> 
> This write function switches on 'reg' and is written assuming
> that these PEC_PCI* constants are valid array indexes...

They should be but...

> > +        break;
> > +    default:
> > +        phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n",
> > __func__,
> > +                      addr, val);
> > +    }
> > +}
> > +++ b/include/hw/pci-host/pnv_phb4.h
> > +struct PnvPhb4PecStatimages/images/e {
> > +    DeviceState parent;
> > +
> > +    /* PEC number in chip */
> > +    uint32_t index;
> > +    uint32_t chip_id;images/
> > +
> > +    MemoryRegion *system_memory;
> > +
> > +    /* Nest registers, excuding per-stack */
> > +#define PHB4_PEC_NEST_REGS_COUNT    0xf
> > +    uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT];
> > +    MemoryRegion nest_regs_mr;
> > +
> > +    /* PCI registers, excluding per-stack */
> > +#define PHB4_PEC_PCI_REGS_COUNT     0x2
> > +    uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT];
> > +    MemoryRegion pci_regs_mr;
> 
> ...but we define the pci_regs[] array in PnvPhb4PecState to
> have only 2 elements...
> 
> > +++ b/include/hw/pci-host/pnv_phb4_regs.h
> > +/* XSCOM PCI global registers */
> > +#define PEC_PCI_PBAIB_HW_CONFIG         0x00
> > +#define PEC_PCI_PBAIB_READ_STK_OVR      0x02
> 
> ...and here we define PEC_PCI_PBAIB_READ_STK_OVR as 2, which makes
> it not a valid index into pci_regs[].
> 
> 
> Which of these is wrong?

This one:

#define PHB4_PEC_PCI_REGS_COUNT     0x2

Should be

#define PHB4_PEC_PCI_REGS_COUNT     0x3

There is no register at 0x1 though.

Cheers,
Ben.



  reply	other threads:[~2022-04-01  2:03 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-03  6:10 [PULL 00/35] ppc-for-5.0 queue 20200203 David Gibson
2020-02-03  6:10 ` [PULL 01/35] ppc/pnv: use QEMU unit definition MiB David Gibson
2020-02-03  6:10 ` [PULL 02/35] ppc/pnv: improve error logging when a PNOR update fails David Gibson
2020-02-03  6:10 ` [PULL 03/35] ppc:virtex_ml507: remove unused arguments David Gibson
2020-02-03  6:10 ` [PULL 04/35] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS David Gibson
2020-02-03  6:10 ` [PULL 05/35] target/ppc: Clarify the meaning of return values in kvm_handle_debug David Gibson
2020-02-03  6:10 ` [PULL 06/35] spapr: Fail CAS if option vector table cannot be parsed David Gibson
2020-03-20 17:38   ` Peter Maydell
2020-02-03  6:10 ` [PULL 07/35] target/ppc: Add privileged message send facilities David Gibson
2020-02-03  6:10 ` [PULL 08/35] target/ppc: add support for Hypervisor Facility Unavailable Exception David Gibson
2020-02-03  6:10 ` [PULL 09/35] spapr: Don't allow multiple active vCPUs at CAS David Gibson
2020-02-03  6:10 ` [PULL 10/35] ppc/pnv: Add support for HRMOR on Radix host David Gibson
2020-02-03  6:10 ` [PULL 11/35] ppc/pnv: remove useless "core-pir" property alias David Gibson
2020-02-03  6:11 ` [PULL 12/35] ppc/pnv: Add support for "hostboot" mode David Gibson
2020-02-03  6:11 ` [PULL 13/35] tpm: Move tpm_tis_show_buffer to tpm_util.c David Gibson
2020-02-03  6:11 ` [PULL 14/35] spapr: Implement get_dt_compatible() callback David Gibson
2020-02-03  6:11 ` [PULL 15/35] tpm_spapr: Support TPM for ppc64 using CRQ based interface David Gibson
2020-02-03  6:11 ` [PULL 16/35] tpm_spapr: Support suspend and resume David Gibson
2020-02-03  6:11 ` [PULL 17/35] hw/ppc/Kconfig: Enable TPM_SPAPR as part of PSERIES config David Gibson
2020-02-03  6:11 ` [PULL 18/35] docs/specs/tpm: reST-ify TPM documentation David Gibson
2020-02-03  6:11 ` [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge David Gibson
2020-02-05 13:26   ` Laurent Vivier
2020-02-05 14:31     ` Greg Kurz
2020-02-05 15:27     ` Cédric Le Goater
2020-02-05 16:29       ` Laurent Vivier
2020-02-05 17:16         ` Cédric Le Goater
2022-03-31 17:51   ` Peter Maydell
2022-04-01  1:59     ` Benjamin Herrenschmidt [this message]
2022-04-01  8:54       ` Frederic Barrat
2020-02-03  6:11 ` [PULL 20/35] ppc/pnv: Add models for POWER8 PHB3 " David Gibson
2020-02-03  6:11 ` [PULL 21/35] ppc/pnv: change the PowerNV machine devices to be non user creatable David Gibson
2020-02-03  6:11 ` [PULL 22/35] spapr: Enable DD2.3 accelerated count cache flush in pseries-5.0 machine David Gibson
2020-02-03  6:11 ` [PULL 23/35] target/ppc/cpu.h: Put macro parameter in parentheses David Gibson
2020-02-03  6:11 ` [PULL 24/35] Wrapper function to wait on condition for the main loop mutex David Gibson
2020-02-03  6:11 ` [PULL 25/35] ppc: spapr: Introduce FWNMI capability David Gibson
2020-02-03  6:11 ` [PULL 26/35] target/ppc: Handle NMI guest exit David Gibson
2020-02-03  6:11 ` [PULL 27/35] target/ppc: Build rtas error log upon an MCE David Gibson
2020-02-03  6:11 ` [PULL 28/35] ppc: spapr: Handle "ibm, nmi-register" and "ibm, nmi-interlock" RTAS calls David Gibson
2020-02-03  6:11 ` [PULL 29/35] migration: Include migration support for machine check handling David Gibson
2020-02-03  6:11 ` [PULL 30/35] ppc: spapr: Activate the FWNMI functionality David Gibson
2020-02-03  6:11 ` [PULL 31/35] target/ppc: Use probe_access for LSW, STSW David Gibson
2020-02-03  6:11 ` [PULL 32/35] target/ppc: Use probe_access for LMW, STMW David Gibson
2020-02-03  6:11 ` [PULL 33/35] target/ppc: Remove redundant mask in DCBZ David Gibson
2020-02-03  6:11 ` [PULL 34/35] target/ppc: Use probe_write for DCBZ David Gibson
2020-02-12 18:48   ` Greg Kurz
2020-02-12 22:36     ` Richard Henderson
2020-02-03  6:11 ` [PULL 35/35] tests: Silence various warnings with pseries David Gibson
2020-02-03 10:41 ` [PULL 00/35] ppc-for-5.0 queue 20200203 Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5b581691e0063d831649b4a6e36f07ef00e42861.camel@kernel.crashing.org \
    --to=benh@kernel.crashing.org \
    --cc=clg@kaod.org \
    --cc=david@gibson.dropbear.id.au \
    --cc=groug@kaod.org \
    --cc=lvivier@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).