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([2001:8004:5170:1e39:8ee2:6e6b:fea2:d3ab]) by smtp.gmail.com with ESMTPSA id y37-20020a634965000000b005ceeeea1816sm4693980pgk.77.2024.01.19.23.37.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jan 2024 23:37:36 -0800 (PST) Message-ID: <5b6571d3-f654-488d-9dc5-0d18ba542e05@linaro.org> Date: Sat, 20 Jan 2024 18:37:27 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking To: Deepak Gupta Cc: Alexey Baturo , zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20240109102930.405323-1-me@deliversmonkey.space> <20240109102930.405323-4-me@deliversmonkey.space> <3cb918ca-27cd-4f1e-8738-306dc5280f42@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/19/24 09:40, Deepak Gupta wrote: > On Thu, Jan 18, 2024 at 12:50 PM Richard Henderson > wrote: >> At some point pointer masking will be in hardware, and the kernel will gain support for >> it, and there will likely be a prctl() added for it. At the point the kernel finalizes >> the API, you will be able to enable pointer masking for qemu-user. > > I am sure I am missing some important detail here, BUT... > > How is it different from aarch64 "top byte ignore". It is very similar, yes. > I think commit: 16c8497 enables top byte ignore for user pointers and > by default for qemu-user for aarch64 target. Not quite, no. commit 0e0c030c681730f3ec55ba3b223b608a8f3e8282 Author: Richard Henderson Date: Fri Feb 12 10:48:51 2021 -0800 linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE is more relevant. > IIRC, user <--> kernel abi is only needed for pointers that are passed > to the kernel. It is also needed to *enable* pointer masking at all. For aarch64, TBI has been enabled for user-space since the beginning, but that is not true for riscv. Therefore there will be a need for a syscall to opt in and enable pointer masking. > And in the case of qemu-user, we are talking about the host kernel. No, we are not. We are always emulating the guest kernel. r~