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From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Delevoryas <peter@pjd.dev>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Andrew Jeffery <andrew@aj.id.au>, Joel Stanley <joel@jms.id.au>,
	<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>
Subject: Re: [PATCH 2/8] aspeed: Create SRAM name from first CPU index
Date: Tue, 5 Jul 2022 07:47:00 +0200	[thread overview]
Message-ID: <5b88331e-fbc5-252f-17c6-6da2dadfc7b7@kaod.org> (raw)
In-Reply-To: <20220704215457.38332-2-peter@pjd.dev>

On 7/4/22 23:54, Peter Delevoryas wrote:
> To support multiple SoC's running simultaneously, we need a unique name for
> each RAM region. DRAM is created by the machine, but SRAM is created by the
> SoC, since in hardware it is part of the SoC's internals.
> 
> We need a way to uniquely identify each SRAM region though, for VM
> migration. Since each of the SoC's CPU's has an index which identifies it
> uniquely from other CPU's in the machine, we can use the index of any of the
> CPU's in the SoC to uniquely identify differentiate the SRAM name from other
> SoC SRAM's. In this change, I just elected to use the index of the first CPU
> in each SoC.
> 
> Signed-off-by: Peter Delevoryas <peter@pjd.dev>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.

> ---
>   hw/arm/aspeed_ast10x0.c | 5 ++++-
>   hw/arm/aspeed_ast2600.c | 5 +++--
>   hw/arm/aspeed_soc.c     | 5 +++--
>   3 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 33ef331771..677699e54c 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -159,6 +159,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
>       DeviceState *armv7m;
>       Error *err = NULL;
>       int i;
> +    g_autofree char *sram_name = NULL;
>   
>       if (!clock_has_source(s->sysclk)) {
>           error_setg(errp, "sysclk clock must be wired up by the board code");
> @@ -183,7 +184,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
>       sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
>   
>       /* Internal SRAM */
> -    memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err);
> +    sram_name = g_strdup_printf("aspeed.sram.%d",
> +                                CPU(s->armv7m.cpu)->cpu_index);
> +    memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
>       if (err != NULL) {
>           error_propagate(errp, err);
>           return;
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index 3f0611ac11..64eb5a7b26 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -276,6 +276,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>       AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>       Error *err = NULL;
>       qemu_irq irq;
> +    g_autofree char *sram_name = NULL;
>   
>       /* IO space */
>       aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
> @@ -335,8 +336,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>       }
>   
>       /* SRAM */
> -    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
> -                           sc->sram_size, &err);
> +    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
> +    memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
>       if (err) {
>           error_propagate(errp, err);
>           return;
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 0f675e7fcd..0bb6a2f092 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -239,6 +239,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
>       AspeedSoCState *s = ASPEED_SOC(dev);
>       AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>       Error *err = NULL;
> +    g_autofree char *sram_name = NULL;
>   
>       /* IO space */
>       aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
> @@ -259,8 +260,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
>       }
>   
>       /* SRAM */
> -    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
> -                           sc->sram_size, &err);
> +    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
> +    memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
>       if (err) {
>           error_propagate(errp, err);
>           return;



  reply	other threads:[~2022-07-05  5:51 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-04 21:54 [PATCH 1/8] hw/i2c/pca954x: Add method to get channels Peter Delevoryas
2022-07-04 21:54 ` [PATCH 2/8] aspeed: Create SRAM name from first CPU index Peter Delevoryas
2022-07-05  5:47   ` Cédric Le Goater [this message]
2022-07-04 21:54 ` [PATCH 3/8] aspeed: Refactor UART init for multi-SoC machines Peter Delevoryas
2022-07-05  5:49   ` Cédric Le Goater
2022-07-04 21:54 ` [PATCH 4/8] aspeed: Make aspeed_board_init_flashes public Peter Delevoryas
2022-07-05  5:49   ` Cédric Le Goater
2022-07-04 21:54 ` [PATCH 5/8] aspeed: Add fby35 skeleton Peter Delevoryas
2022-07-05  6:53   ` Joel Stanley
2022-07-05  7:58     ` Peter Delevoryas
2022-07-05  8:09       ` Cédric Le Goater
2022-07-04 21:54 ` [PATCH 6/8] aspeed: Add AST2600 (BMC) to fby35 Peter Delevoryas
2022-07-05  5:49   ` Cédric Le Goater
2022-07-04 21:54 ` [PATCH 7/8] aspeed: fby35: Add a bootrom for the BMC Peter Delevoryas
2022-07-04 21:54 ` [PATCH 8/8] aspeed: Add AST1030 (BIC) to fby35 Peter Delevoryas
2022-07-05  5:50   ` Cédric Le Goater
2022-07-05  5:46 ` [PATCH 1/8] hw/i2c/pca954x: Add method to get channels Cédric Le Goater
2022-07-06 16:41   ` Patrick Venture

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