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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9df99d3sm83068815e9.12.2025.11.21.04.49.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Nov 2025 04:49:37 -0800 (PST) Message-ID: <5ba8afd2-676a-4aee-ac9c-b8d0fdf8d826@redhat.com> Date: Fri, 21 Nov 2025 13:49:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC v3 04/21] refactor: Move ARMSecuritySpace to a common header Content-Language: en-US To: Tao Tang , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh References: <20251012150701.4127034-1-tangtao1634@phytium.com.cn> <20251012150701.4127034-5-tangtao1634@phytium.com.cn> From: Eric Auger In-Reply-To: <20251012150701.4127034-5-tangtao1634@phytium.com.cn> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/12/25 5:06 PM, Tao Tang wrote: > The ARMSecuritySpace enum and its related helpers were defined in the > target-specific header target/arm/cpu.h. This prevented common, > target-agnostic code like the SMMU model from using these definitions > without triggering "cpu.h included from common code" errors. > > To resolve this, this commit introduces a new, lightweight header, > include/hw/arm/arm-security.h, which is safe for inclusion by common > code. > > The following change was made: > > - The ARMSecuritySpace enum and the arm_space_is_secure() and > arm_secure_to_space() helpers have been moved from target/arm/cpu.h > to the new hw/arm/arm-security.h header. > > This refactoring decouples the security state definitions from the core > CPU implementation, allowing common hardware models to correctly handle > security states without pulling in heavyweight, target-specific headers. > > Signed-off-by: Tao Tang > Reviewed-by: Eric Auger nit: the commit msg prefix is unusual (refactor). I would rename into target/arm: Move ARMSecuritySpace to a common header Eric > Link: https://lists.nongnu.org/archive/html/qemu-arm/2025-09/msg01288.html > --- > include/hw/arm/arm-security.h | 54 +++++++++++++++++++++++++++++++++++ > target/arm/cpu.h | 25 +--------------- > 2 files changed, 55 insertions(+), 24 deletions(-) > create mode 100644 include/hw/arm/arm-security.h > > diff --git a/include/hw/arm/arm-security.h b/include/hw/arm/arm-security.h > new file mode 100644 > index 0000000000..9664c0f95e > --- /dev/null > +++ b/include/hw/arm/arm-security.h > @@ -0,0 +1,54 @@ > +/* > + * ARM security space helpers > + * > + * Provide ARMSecuritySpace and helpers for code that is not tied to CPU. > + * > + * Copyright (c) 2003 Fabrice Bellard > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#ifndef HW_ARM_ARM_SECURITY_H > +#define HW_ARM_ARM_SECURITY_H > + > +#include > + > +/* > + * ARM v9 security states. > + * The ordering of the enumeration corresponds to the low 2 bits > + * of the GPI value, and (except for Root) the concat of NSE:NS. > + */ > + > + typedef enum ARMSecuritySpace { > + ARMSS_Secure = 0, > + ARMSS_NonSecure = 1, > + ARMSS_Root = 2, > + ARMSS_Realm = 3, > +} ARMSecuritySpace; > + > +/* Return true if @space is secure, in the pre-v9 sense. */ > +static inline bool arm_space_is_secure(ARMSecuritySpace space) > +{ > + return space == ARMSS_Secure || space == ARMSS_Root; > +} > + > +/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ > +static inline ARMSecuritySpace arm_secure_to_space(bool secure) > +{ > + return secure ? ARMSS_Secure : ARMSS_NonSecure; > +} > + > +#endif /* HW_ARM_ARM_SECURITY_H */ > + > + > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 1d4e13320c..3336d95c6a 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -31,6 +31,7 @@ > #include "exec/page-protection.h" > #include "qapi/qapi-types-common.h" > #include "target/arm/multiprocessing.h" > +#include "hw/arm/arm-security.h" > #include "target/arm/gtimer.h" > #include "target/arm/cpu-sysregs.h" > #include "target/arm/mmuidx.h" > @@ -2098,30 +2099,6 @@ static inline int arm_feature(CPUARMState *env, int feature) > > void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); > > -/* > - * ARM v9 security states. > - * The ordering of the enumeration corresponds to the low 2 bits > - * of the GPI value, and (except for Root) the concat of NSE:NS. > - */ > - > -typedef enum ARMSecuritySpace { > - ARMSS_Secure = 0, > - ARMSS_NonSecure = 1, > - ARMSS_Root = 2, > - ARMSS_Realm = 3, > -} ARMSecuritySpace; > - > -/* Return true if @space is secure, in the pre-v9 sense. */ > -static inline bool arm_space_is_secure(ARMSecuritySpace space) > -{ > - return space == ARMSS_Secure || space == ARMSS_Root; > -} > - > -/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ > -static inline ARMSecuritySpace arm_secure_to_space(bool secure) > -{ > - return secure ? ARMSS_Secure : ARMSS_NonSecure; > -} > > #if !defined(CONFIG_USER_ONLY) > /**