From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
Aurelien Jarno <aurelien@aurel32.net>,
Mateja Marjanovic <mateja.marjanovic@rt-rk.com>,
"Maciej W . Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH-for-5.2?] target/mips/translate: Check R6 reserved encoding for Load Linked Word
Date: Tue, 24 Nov 2020 07:59:06 -0800 [thread overview]
Message-ID: <5bcade19-de8c-8521-f77c-599e3c9d40a0@linaro.org> (raw)
In-Reply-To: <20201124134557.569388-1-f4bug@amsat.org>
On 11/24/20 5:45 AM, Philippe Mathieu-Daudé wrote:
> Release 6 recoded the 'Load Linked Word' using SPECIAL3 opcode,
> this opcode (0b110000) is now reserved.
>
> Ref: A.2 Instruction Bit Encoding Tables:
>
> "6Rm instructions signal a Reserved Instruction exception
> when executed by a Release 6 implementation."
>
> The check was added in commit 4368b29a26e ("target-mips: move
> LL and SC instructions") but got lost during latter refactor
> in commit d9224450208 ("target-mips: Tighten ISA level checks").
I think git blame is confused here -- d9224450208 isn't the one that broke
things. The patch has:
+ case OPC_LL: /* Load and stores */
+ check_insn(ctx, ISA_MIPS2);
+ /* Fallthrough */
+ case OPC_LWL:
case OPC_LWR:
- case OPC_LL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ /* Fallthrough */
Whereever it happened, it's broken now, so
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-11-24 16:00 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-24 13:45 [PATCH-for-5.2?] target/mips/translate: Check R6 reserved encoding for Load Linked Word Philippe Mathieu-Daudé
2020-11-24 15:59 ` Richard Henderson [this message]
2020-11-24 16:15 ` Philippe Mathieu-Daudé
2020-12-08 18:34 ` Philippe Mathieu-Daudé
2020-12-08 18:43 ` Maciej W. Rozycki
2020-12-08 19:12 ` Philippe Mathieu-Daudé
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