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Tue, 24 Nov 2020 07:59:10 -0800 (PST) Received: from [192.168.1.11] ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id o89sm3763398pjo.47.2020.11.24.07.59.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Nov 2020 07:59:09 -0800 (PST) Subject: Re: [PATCH-for-5.2?] target/mips/translate: Check R6 reserved encoding for Load Linked Word To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org References: <20201124134557.569388-1-f4bug@amsat.org> From: Richard Henderson Message-ID: <5bcade19-de8c-8521-f77c-599e3c9d40a0@linaro.org> Date: Tue, 24 Nov 2020 07:59:06 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201124134557.569388-1-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Aurelien Jarno , Mateja Marjanovic , "Maciej W . Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/24/20 5:45 AM, Philippe Mathieu-Daudé wrote: > Release 6 recoded the 'Load Linked Word' using SPECIAL3 opcode, > this opcode (0b110000) is now reserved. > > Ref: A.2 Instruction Bit Encoding Tables: > > "6Rm instructions signal a Reserved Instruction exception > when executed by a Release 6 implementation." > > The check was added in commit 4368b29a26e ("target-mips: move > LL and SC instructions") but got lost during latter refactor > in commit d9224450208 ("target-mips: Tighten ISA level checks"). I think git blame is confused here -- d9224450208 isn't the one that broke things. The patch has: + case OPC_LL: /* Load and stores */ + check_insn(ctx, ISA_MIPS2); + /* Fallthrough */ + case OPC_LWL: case OPC_LWR: - case OPC_LL: check_insn_opc_removed(ctx, ISA_MIPS32R6); + /* Fallthrough */ Whereever it happened, it's broken now, so Reviewed-by: Richard Henderson r~