Re: [PATCH] target/hppa: correct size bit parity for fmpyadd

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 9/10/25 22:51, Gabriel Brookman wrote:
> For the fmpyadd instruction on the hppa architecture, there is a bit
> used to specify whether the instruction is operating on a 32 bit or 64
> bit floating point register. For most instructions, such a bit is 0 when
> operating on the smaller register and 1 when operating on the larger
> register. However, according to page 6-57 of the PA-RISC 1.1 Architecture
> and Instruction Set Reference Manual, this convention is reversed for the
> fmpyadd instruction specifically, meaning the bit is 1 for operations on
> 32 bit registers and 0 for 64 bit registers. Previously, QEMU decoded
> this operation as operating on the other size of register, leading to
> bugs when translating the fmpyadd instruction. This patch fixes that
> issue.
> 
> Reported-by: Andreas Hüttel <andreas.huettel@ur.de>
> Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3096
> ---
> Hi all,
> 
> This patch fixes the decoding of the fmpyadd instruction on the hppa
> target, which uses an inverted bit convention to select between
> 32-bit and 64-bit floating-point registers. The issue was reported by
> Andreas Hüttel after observing incorrect behavior when running real
> binaries under that target. He kindly submitted a minimal reproducer
> which I was able to use to debug the issue. I used this reproducer
> to verify correct operation after my fix.
> 
> Thanks,
> Gabriel
> 
> Reported-by: Andreas Hüttel
> ---
>   target/hppa/insns.decode | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)

Patch queued (including doc refs Andreas added).