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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id z7sm11101260pfe.194.2021.10.30.20.41.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Oct 2021 20:41:39 -0700 (PDT) Subject: Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211025122818.168890-1-frederic.petrot@univ-grenoble-alpes.fr> <20211025122818.168890-9-frederic.petrot@univ-grenoble-alpes.fr> From: Richard Henderson Message-ID: <5bfc385d-03f7-2b4c-f0cb-4f07c844f3f5@linaro.org> Date: Sat, 30 Oct 2021 20:41:37 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211025122818.168890-9-frederic.petrot@univ-grenoble-alpes.fr> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.426, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/25/21 5:28 AM, Frédéric Pétrot wrote: > diff --git a/configs/targets/riscv128-softmmu.mak b/configs/targets/riscv128-softmmu.mak > index a9343d57d3..41daab1cd3 100644 > --- a/configs/targets/riscv128-softmmu.mak > +++ b/configs/targets/riscv128-softmmu.mak > @@ -1,5 +1,6 @@ > TARGET_ARCH=riscv128 > TARGET_BASE_ARCH=riscv > -TARGET_SUPPORTS_MTTCG=y > +# As long as we have no atomic accesses for aligned 128-bit addresses > +TARGET_SUPPORTS_MTTCG=n Ah yes, this is why you need the separate executable, at least in the short-term. We should be able to fix this on the tcg side at some point. This hunk should be folded back to patch 6. > +static TCGv dest_gprh(DisasContext *ctx, int reg_num) > +{ > + if (reg_num == 0 || get_ol(ctx) < MXL_RV128) { > + return temp_new(ctx); > + } > + return cpu_gprh[reg_num]; > +} You don't need to check get_ol here. > + if (get_ol(ctx) != MXL_RV128) { > + g_assert_not_reached(); > + } This is assert. > + if (a->imm != 0) { > + tcg_gen_addi_tl(addrl, src1l, a->imm); > + } else { > + tcg_gen_mov_tl(addrl, src1l); > + } tcg_gen_addi_tl contains exactly this check; remove it here. Two instances. r~