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From: Richard Henderson <richard.henderson@linaro.org>
To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	david@gibson.dropbear.id.au
Subject: Re: [Qemu-devel] [PATCH 8/8] target/ppc: simplify get_cpu_vsrh() and get_cpu_vsrl() functions
Date: Sun, 3 Mar 2019 15:35:18 -0800	[thread overview]
Message-ID: <5c37085e-2c33-32d0-235c-76a9100d4bbf@linaro.org> (raw)
In-Reply-To: <20190303172343.13406-9-mark.cave-ayland@ilande.co.uk>

On 3/3/19 9:23 AM, Mark Cave-Ayland wrote:
>  static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
>  {
> -    if (n < 32) {
> -        get_fpr(dst, n);
> -    } else {
> -        get_avr64(dst, n - 32, true);
> -    }
> +    tcg_gen_ld_i64(dst, cpu_env, vsrh_offset(n));
>  }
>  
>  static inline void get_cpu_vsrl(TCGv_i64 dst, int n)
>  {
> -    if (n < 32) {
> -        get_vsrl(dst, n);
> -    } else {
> -        get_avr64(dst, n - 32, false);
> -    }
> +    tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n));
>  }
>  
>  static inline void set_cpu_vsrh(int n, TCGv_i64 src)
>  {
> -    if (n < 32) {
> -        set_fpr(n, src);
> -    } else {
> -        set_avr64(n - 32, src, true);
> -    }
> +    tcg_gen_st_i64(src, cpu_env, vsrh_offset(n));
>  }

I think these ought to have a "high" parameter, like set/get_avr64.


r~

  reply	other threads:[~2019-03-03 23:35 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-03 17:23 [Qemu-devel] [PATCH 0/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order Mark Cave-Ayland
2019-03-03 17:23 ` [Qemu-devel] [PATCH 1/8] target/ppc: introduce single fpr_offset() function Mark Cave-Ayland
2019-03-03 23:19   ` Richard Henderson
2019-03-04  5:37   ` David Gibson
2019-03-03 17:23 ` [Qemu-devel] [PATCH 2/8] target/ppc: introduce single vsrl_offset() function Mark Cave-Ayland
2019-03-03 23:20   ` Richard Henderson
2019-03-04  5:39   ` David Gibson
2019-03-03 17:23 ` [Qemu-devel] [PATCH 3/8] target/ppc: move Vsr* macros from internal.h to cpu.h Mark Cave-Ayland
2019-03-03 17:23 ` [Qemu-devel] [PATCH 4/8] target/ppc: introduce avrh_offset() and avrl_offset() functions Mark Cave-Ayland
2019-03-03 23:31   ` Richard Henderson
2019-03-05 17:38     ` Mark Cave-Ayland
2019-03-05 21:24       ` Richard Henderson
2019-03-03 17:23 ` [Qemu-devel] [PATCH 5/8] target/ppc: introduce avr_offset() function Mark Cave-Ayland
2019-03-03 23:29   ` Richard Henderson
2019-03-05 17:16     ` Mark Cave-Ayland
2019-03-05 21:16       ` Richard Henderson
2019-03-03 17:23 ` [Qemu-devel] [PATCH 6/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order Mark Cave-Ayland
2019-03-03 23:32   ` Richard Henderson
2019-03-03 17:23 ` [Qemu-devel] [PATCH 7/8] target/ppc: introduce vsrh_offset() function Mark Cave-Ayland
2019-03-03 23:33   ` Richard Henderson
2019-03-05 17:42     ` Mark Cave-Ayland
2019-03-03 17:23 ` [Qemu-devel] [PATCH 8/8] target/ppc: simplify get_cpu_vsrh() and get_cpu_vsrl() functions Mark Cave-Ayland
2019-03-03 23:35   ` Richard Henderson [this message]
2019-03-05 18:16     ` Mark Cave-Ayland
2019-03-06 21:48       ` [Qemu-devel] [Qemu-ppc] " Mark Cave-Ayland
2019-03-06 22:27         ` Richard Henderson
2019-03-04  5:43 ` [Qemu-devel] [PATCH 0/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order David Gibson

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