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Fri, 01 Aug 2025 06:08:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG8sAkdjVG5AKkSbHvHgjfV5/FX8QD5zeHg5PiML0eIFX//aI8KxDHnqA0WUafWcpNX4/3oTQ== X-Received: by 2002:a05:600c:c4a3:b0:450:6b55:cf91 with SMTP id 5b1f17b1804b1-45892b94d5emr99858465e9.6.1754053693987; Fri, 01 Aug 2025 06:08:13 -0700 (PDT) Received: from [192.168.10.81] ([176.206.122.191]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-458981d0b06sm108768545e9.5.2025.08.01.06.08.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 01 Aug 2025 06:08:13 -0700 (PDT) Message-ID: <5c73f6ef-7a6b-42ed-ab79-9060471f1891@redhat.com> Date: Fri, 1 Aug 2025 15:08:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 6/6] kvm: i386: irqchip: take BQL only if there is an interrupt To: Igor Mammedov , Peter Xu Cc: qemu-devel@nongnu.org, mst@redhat.com, mtosatti@redhat.com, kraxel@redhat.com, peter.maydell@linaro.org References: <20250730123934.1787379-1-imammedo@redhat.com> <20250730123934.1787379-7-imammedo@redhat.com> <20250801104215.2ceaa19a@fedora> From: Paolo Bonzini Content-Language: en-US Autocrypt: addr=pbonzini@redhat.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/1/25 10:42, Igor Mammedov wrote: > looking at the code, it seems we are always hold BQL when setting > exit_request. While the BQL is taken, it is for other reasons (e.g. because of cpu->halt_cond). In this case it's set and read from within the same thread so it's okay. > it matches with similar pattern: > > /* Read cpu->exit_request before KVM_RUN reads run->immediate_exit. > * Matching barrier in kvm_eat_signals. > */ > smp_rmb(); > > run_ret = kvm_vcpu_ioctl(cpu, KVM_RUN, 0); > > to be on the safe side, this is preserving barrier that BQL has provided before > I can drop it if it's not really needed. That comment is wrong... The actual pairing here is with cpu_exit(), though the logic of cpu_exit() is messed up and only fully works for TCG, and immediate_exit does not matter at all. I'll clean it up and write a comment. A correct ordering would be: (a) store other flags that will be checked if cpu->exit_request is 1 (b) cpu_exit(): store-release cpu->exit_request (c) cpu_interrupt(): store-release cpu->interrupt_request - broadcast cpu->halt_cond if needed; right now it's done always in qemu_cpu_kick() >>> now you can release the BQL (d) do the accelerator-specific kick (e.g. write icount_decr for TCG, pthread_kill for KVM, etc.) The other side then does the checks in the opposite direction: (d) the accelerator's execution loop exits thanks to the kick (c) then check cpu->interrupt_request - any work that's needed here may take the BQL or not, and may set cpu->exit_request (b) then check cpu->exit_request to see if it should do slow path work (a) then (under the BQL) it possibly goes to sleep, waiting on cpu->halt_cond. cpu->exit_request and cpu->interrupt_request are not a load-acquire/store-release pair right now, but it should be. Probably everything is protected one way or the other by the BQL, but it's not clear. I'll handle cpu->exit_request and leave cpu->interrupt_request to you. For the sake of this series, please do the following: - contrarily to what I said in my earlier review, do introduce a cpu_test_interrupt() now and make it use a load-acquire. There aren't many occurrences: accel/tcg/cpu-exec.c: if (unlikely(qatomic_read(&cpu->interrupt_request))) { target/alpha/cpu.c: return cs->interrupt_request & (CPU_INTERRUPT_HARD target/arm/cpu.c: && cs->interrupt_request & target/arm/hvf/hvf.c: if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { target/avr/cpu.c: return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) target/hppa/cpu.c: return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); target/i386/kvm/kvm.c: if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { target/i386/kvm/kvm.c: if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { target/i386/nvmm/nvmm-all.c: if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { target/i386/whpx/whpx-all.c: cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { target/i386/whpx/whpx-all.c: if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { target/microblaze/cpu.c: return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); target/openrisc/cpu.c: return cs->interrupt_request & (CPU_INTERRUPT_HARD | target/rx/cpu.c: return cs->interrupt_request & - in tcg_handle_interrupt and generic_handle_interrupt, change like this /* Pairs with load_acquire in cpu_test_interrupt(). */ qatomic_store_release(&cpu->interrupt_request, cpu->interrupt_request | mask); I'll take care of properly adding the store-release/load-acquire for exit_request and removing the unnecessary memory barriers in kvm-all.c. Paolo >> >> Thanks, >> >>> + } >>> >>> + if (release_bql) { >>> bql_unlock(); >>> } >>> } >>> -- >>> 2.47.1 >>> >> > > >