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From: Richard Henderson <richard.henderson@linaro.org>
To: Taylor Simpson <tsimpson@quicinc.com>, qemu-devel@nongnu.org
Cc: philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com,
	quic_mathbern@quicinc.com
Subject: Re: [PATCH 11/21] Hexagon (target/hexagon) Short-circuit packet register writes
Date: Thu, 27 Apr 2023 11:40:14 +0100	[thread overview]
Message-ID: <5ca8d1de-319c-4a2e-51ec-c9dd0a1f9727@linaro.org> (raw)
In-Reply-To: <20230426004234.1319401-2-tsimpson@quicinc.com>

On 4/26/23 01:42, Taylor Simpson wrote:
> In certain cases, we can avoid the overhead of writing to hex_new_value
> and write directly to hex_gpr.  We add need_commit field to DisasContext
> indicating if the end-of-packet commit is needed.  If it is not needed,
> get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
> 
> We pass the ctx->need_commit to helpers when needed.
> 
> Finally, we can early-exit from gen_reg_writes during packet commit.
> 
> There are a few instructions whose semantics write to the result before
> reading all the inputs.  Therefore, the idef-parser generated code is
> incompatible with short-circuit.  We tell idef-parser to skip them.
> 
> For debugging purposes, we add a cpu property to turn off short-circuit.
> When the short-circuit property is false, we skip the analysis and force
> the end-of-packet commit.
> 
> Here's a simple example of the TCG generated for
> 0x004000b4:  0x7800c020 {       R0 = #0x1 }
> 
> BEFORE:
>   ---- 004000b4
>   movi_i32 new_r0,$0x1
>   mov_i32 r0,new_r0
> 
> AFTER:
>   ---- 004000b4
>   movi_i32 r0,$0x1
> 
> Signed-off-by: Taylor Simpson<tsimpson@quicinc.com>
> ---

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


  reply	other threads:[~2023-04-27 10:40 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-26  0:42 [PATCH 10/21] Hexagon (target/hexagon) Mark registers as read during packet analysis Taylor Simpson
2023-04-26  0:42 ` [PATCH 11/21] Hexagon (target/hexagon) Short-circuit packet register writes Taylor Simpson
2023-04-27 10:40   ` Richard Henderson [this message]
2023-04-26  0:42 ` [PATCH 12/21] Hexagon (target/hexagon) Short-circuit packet predicate writes Taylor Simpson
2023-04-27 10:41   ` Richard Henderson
2023-04-26  0:42 ` [PATCH 13/21] Hexagon (target/hexagon) Short-circuit packet HVX writes Taylor Simpson
2023-04-27 10:42   ` Richard Henderson
2023-04-26  0:42 ` [PATCH 14/21] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets Taylor Simpson
2023-04-27 10:44   ` Richard Henderson
2023-04-26  0:42 ` [PATCH 15/21] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns Taylor Simpson
2023-04-27 10:52   ` Richard Henderson
2023-04-26  0:42 ` [PATCH 16/21] Hexagon (target/hexagon) Make special new_value for USR Taylor Simpson
2023-04-27 10:57   ` Richard Henderson
2023-04-26  0:42 ` [PATCH 17/21] Hexagon (target/hexagon) Move new_value to DisasContext Taylor Simpson
2023-04-27 11:01   ` Richard Henderson
2023-04-27 11:03     ` Richard Henderson
2023-04-26  0:42 ` [PATCH 18/21] Hexagon (target/hexagon) Move new_pred_value " Taylor Simpson
2023-04-27 11:03   ` Richard Henderson
2023-04-26  0:42 ` [PATCH 19/21] Hexagon (target/hexagon) Move pred_written " Taylor Simpson
2023-04-27 11:05   ` Richard Henderson
2023-04-27  8:04 ` [PATCH 10/21] Hexagon (target/hexagon) Mark registers as read during packet analysis Richard Henderson

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