[Qemu-devel] [PATCH v1 0/3] s390x: SIGP + IRQ preparations for TCG vector register support

[Qemu-devel] [PATCH v1 0/3] s390x: SIGP + IRQ preparations for TCG vector register support

[David Hildenbrand]

These are minor preparations for vector instruction support for TCG, also
touching KVM code.

During SIGP STORE ADDITIONAL STATUS we have to properly convert the
endianess. On machine checks, we have to also store the vector registers
into the extended save area.

Both changes are not used by TCG code before we implement + enable
vector instructions. KVM code shares the SIGP STORE ADDITIONAL STATUS
implementation.

Note: Vector registers (128 bit) are modeled as two 64 bit values. Low and
high 64 bit values correspond on big/little systems, however the values
themself need conversion. Documentation for that will be added along with
the actual vector instruction support.

David Hildenbrand (3):
  s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS
  s390x: use a QEMU-style typedef + name for SIGP save area struct
  s390x/tcg: Save vregs to extended mchk save area

 target/s390x/excp_helper.c | 46 ++++++++++++++++++++++++++++++++++++--
 target/s390x/helper.c      | 39 ++++++++++++++++++++------------
 target/s390x/internal.h    |  4 +++-
 3 files changed, 72 insertions(+), 17 deletions(-)

-- 
2.17.2

[Qemu-devel] [PATCH v1 1/3] s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS

[David Hildenbrand]

As we will support vector instructions soon, and vector registers are
stored in 64bit host chunks, let's use cpu_to_be64. Same applies to the
guarded storage control block.

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/helper.c | 31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index 3d74836a83..f3fcf96482 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -272,32 +272,43 @@ int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
     return 0;
 }
 
-#define ADTL_GS_OFFSET   1024 /* offset of GS data in adtl save area */
+typedef struct SigpAdtlSaveArea {
+    uint64_t    vregs[32][2];                     /* 0x0000 */
+    uint8_t     pad_0x0200[0x0400 - 0x0200];      /* 0x0200 */
+    uint64_t    gscb[4];                          /* 0x0400 */
+    uint8_t     pad_0x0420[0x1000 - 0x0420];      /* 0x0420 */
+} SigpAdtlSaveArea;
+QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096);
+
 #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
 int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
 {
+    SigpAdtlSaveArea *sa;
     hwaddr save = len;
-    void *mem;
+    int i;
 
-    mem = cpu_physical_memory_map(addr, &save, 1);
-    if (!mem) {
+    sa = cpu_physical_memory_map(addr, &save, 1);
+    if (!sa) {
         return -EFAULT;
     }
     if (save != len) {
-        cpu_physical_memory_unmap(mem, len, 1, 0);
+        cpu_physical_memory_unmap(sa, len, 1, 0);
         return -EFAULT;
     }
 
-    /* FIXME: as soon as TCG supports these features, convert cpu->be */
     if (s390_has_feat(S390_FEAT_VECTOR)) {
-        memcpy(mem, &cpu->env.vregs, 512);
+        for (i = 0; i < 32; i++) {
+            sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0].ll);
+            sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1].ll);
+        }
     }
     if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
-        memcpy(mem + ADTL_GS_OFFSET, &cpu->env.gscb, 32);
+        for (i = 0; i < 4; i++) {
+            sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]);
+        }
     }
 
-    cpu_physical_memory_unmap(mem, len, 1, len);
-
+    cpu_physical_memory_unmap(sa, len, 1, len);
     return 0;
 }
 #endif /* CONFIG_USER_ONLY */
-- 
2.17.2

[Qemu-devel] [PATCH v1 2/3] s390x: use a QEMU-style typedef + name for SIGP save area struct

[David Hildenbrand]

Convert this to QEMU style.

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/helper.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index f3fcf96482..a7edd5df7d 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -211,7 +211,7 @@ void s390_cpu_recompute_watchpoints(CPUState *cs)
     }
 }
 
-struct sigp_save_area {
+typedef struct SigpSaveArea {
     uint64_t    fprs[16];                       /* 0x0000 */
     uint64_t    grs[16];                        /* 0x0080 */
     PSW         psw;                            /* 0x0100 */
@@ -225,13 +225,13 @@ struct sigp_save_area {
     uint8_t     pad_0x0138[0x0140 - 0x0138];    /* 0x0138 */
     uint32_t    ars[16];                        /* 0x0140 */
     uint64_t    crs[16];                        /* 0x0384 */
-};
-QEMU_BUILD_BUG_ON(sizeof(struct sigp_save_area) != 512);
+} SigpSaveArea;
+QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512);
 
 int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
 {
     static const uint8_t ar_id = 1;
-    struct sigp_save_area *sa;
+    SigpSaveArea *sa;
     hwaddr len = sizeof(*sa);
     int i;
 
-- 
2.17.2

[Qemu-devel] [PATCH v1 3/3] s390x/tcg: Save vregs to extended mchk save area

[David Hildenbrand]

If we have vector registers and the designation is not zero, we have
to try to write the vector registers. If the designation is zero or
if storing fails, we must not indicate validity. s390_build_validity_mcic()
automatically already sets validity if the vector instruction facility
is installed.

As long as we don't support the guarded-storage facility, the alignemnt &
size of the area is always 1024 bytes.

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/excp_helper.c | 46 ++++++++++++++++++++++++++++++++++++--
 target/s390x/internal.h    |  4 +++-
 2 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index a758649f47..f84bfb1284 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -347,10 +347,41 @@ static void do_io_interrupt(CPUS390XState *env)
     load_psw(env, mask, addr);
 }
 
+typedef struct MchkExtSaveArea {
+    uint64_t    vregs[32][2];                     /* 0x0000 */
+    uint8_t     pad_0x0200[0x0400 - 0x0200];      /* 0x0200 */
+} MchkExtSaveArea;
+QEMU_BUILD_BUG_ON(sizeof(MchkExtSaveArea) != 1024);
+
+static int mchk_store_vregs(CPUS390XState *env, uint64_t mcesao)
+{
+    hwaddr len = sizeof(MchkExtSaveArea);
+    MchkExtSaveArea *sa;
+    int i;
+
+    sa = cpu_physical_memory_map(mcesao, &len, 1);
+    if (!sa) {
+        return -EFAULT;
+    }
+    if (len != sizeof(MchkExtSaveArea)) {
+        cpu_physical_memory_unmap(sa, len, 1, 0);
+        return -EFAULT;
+    }
+
+    for (i = 0; i < 32; i++) {
+        sa->vregs[i][0] = cpu_to_be64(env->vregs[i][0].ll);
+        sa->vregs[i][1] = cpu_to_be64(env->vregs[i][1].ll);
+    }
+
+    cpu_physical_memory_unmap(sa, len, 1, len);
+    return 0;
+}
+
 static void do_mchk_interrupt(CPUS390XState *env)
 {
     QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic());
-    uint64_t mask, addr;
+    uint64_t mcic = s390_build_validity_mcic() | MCIC_SC_CP;
+    uint64_t mask, addr, mcesao = 0;
     LowCore *lowcore;
     int i;
 
@@ -362,6 +393,17 @@ static void do_mchk_interrupt(CPUS390XState *env)
 
     lowcore = cpu_map_lowcore(env);
 
+    /* extended save area */
+    if (mcic & MCIC_VB_VR) {
+        /* length and alignment is 1024 bytes */
+        mcesao = be64_to_cpu(lowcore->mcesad) & ~0x3ffull;
+    }
+
+    /* try to store vector registers */
+    if (!mcesao || mchk_store_vregs(env, mcesao)) {
+        mcic &= ~MCIC_VB_VR;
+    }
+
     /* we are always in z/Architecture mode */
     lowcore->ar_access_id = 1;
 
@@ -377,7 +419,7 @@ static void do_mchk_interrupt(CPUS390XState *env)
     lowcore->cpu_timer_save_area = cpu_to_be64(env->cputm);
     lowcore->clock_comp_save_area = cpu_to_be64(env->ckc >> 8);
 
-    lowcore->mcic = cpu_to_be64(s390_build_validity_mcic() | MCIC_SC_CP);
+    lowcore->mcic = cpu_to_be64(mcic);
     lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
     lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
     mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 122fe037bc..cbeef3515b 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -101,7 +101,9 @@ typedef struct LowCore {
     /* whether the kernel died with panic() or not */
     uint32_t        panic_magic;              /* 0xe00 */
 
-    uint8_t         pad13[0x11b8 - 0xe04];    /* 0xe04 */
+    uint8_t         pad13[0x11b0 - 0xe04];    /* 0xe04 */
+
+    uint64_t        mcesad;                    /* 0x11B0 */
 
     /* 64 bit extparam used for pfault, diag 250 etc  */
     uint64_t        ext_params2;               /* 0x11B8 */
-- 
2.17.2

Re: [Qemu-devel] [PATCH v1 2/3] s390x: use a QEMU-style typedef + name for SIGP save area struct

[Thomas Huth]

On 22/02/2019 09.11, David Hildenbrand wrote:
> Convert this to QEMU style.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
>  target/s390x/helper.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/s390x/helper.c b/target/s390x/helper.c
> index f3fcf96482..a7edd5df7d 100644
> --- a/target/s390x/helper.c
> +++ b/target/s390x/helper.c
> @@ -211,7 +211,7 @@ void s390_cpu_recompute_watchpoints(CPUState *cs)
>      }
>  }
>  
> -struct sigp_save_area {
> +typedef struct SigpSaveArea {
>      uint64_t    fprs[16];                       /* 0x0000 */
>      uint64_t    grs[16];                        /* 0x0080 */
>      PSW         psw;                            /* 0x0100 */
> @@ -225,13 +225,13 @@ struct sigp_save_area {
>      uint8_t     pad_0x0138[0x0140 - 0x0138];    /* 0x0138 */
>      uint32_t    ars[16];                        /* 0x0140 */
>      uint64_t    crs[16];                        /* 0x0384 */
> -};
> -QEMU_BUILD_BUG_ON(sizeof(struct sigp_save_area) != 512);
> +} SigpSaveArea;
> +QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512);
>  
>  int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
>  {
>      static const uint8_t ar_id = 1;
> -    struct sigp_save_area *sa;
> +    SigpSaveArea *sa;
>      hwaddr len = sizeof(*sa);
>      int i;

Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [Qemu-devel] [PATCH v1 1/3] s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS

[Thomas Huth]

On 22/02/2019 09.11, David Hildenbrand wrote:
> As we will support vector instructions soon, and vector registers are
> stored in 64bit host chunks, let's use cpu_to_be64. Same applies to the
> guarded storage control block.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
>  target/s390x/helper.c | 31 +++++++++++++++++++++----------
>  1 file changed, 21 insertions(+), 10 deletions(-)
> 
> diff --git a/target/s390x/helper.c b/target/s390x/helper.c
> index 3d74836a83..f3fcf96482 100644
> --- a/target/s390x/helper.c
> +++ b/target/s390x/helper.c
> @@ -272,32 +272,43 @@ int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
>      return 0;
>  }
>  
> -#define ADTL_GS_OFFSET   1024 /* offset of GS data in adtl save area */
> +typedef struct SigpAdtlSaveArea {
> +    uint64_t    vregs[32][2];                     /* 0x0000 */
> +    uint8_t     pad_0x0200[0x0400 - 0x0200];      /* 0x0200 */
> +    uint64_t    gscb[4];                          /* 0x0400 */
> +    uint8_t     pad_0x0420[0x1000 - 0x0420];      /* 0x0420 */
> +} SigpAdtlSaveArea;
> +QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096);
> +
>  #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
>  int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
>  {
> +    SigpAdtlSaveArea *sa;
>      hwaddr save = len;
> -    void *mem;
> +    int i;
>  
> -    mem = cpu_physical_memory_map(addr, &save, 1);
> -    if (!mem) {
> +    sa = cpu_physical_memory_map(addr, &save, 1);
> +    if (!sa) {
>          return -EFAULT;
>      }
>      if (save != len) {
> -        cpu_physical_memory_unmap(mem, len, 1, 0);
> +        cpu_physical_memory_unmap(sa, len, 1, 0);
>          return -EFAULT;
>      }
>  
> -    /* FIXME: as soon as TCG supports these features, convert cpu->be */
>      if (s390_has_feat(S390_FEAT_VECTOR)) {
> -        memcpy(mem, &cpu->env.vregs, 512);
> +        for (i = 0; i < 32; i++) {
> +            sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0].ll);
> +            sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1].ll);
> +        }
>      }
>      if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
> -        memcpy(mem + ADTL_GS_OFFSET, &cpu->env.gscb, 32);
> +        for (i = 0; i < 4; i++) {
> +            sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]);
> +        }
>      }
>  
> -    cpu_physical_memory_unmap(mem, len, 1, len);
> -
> +    cpu_physical_memory_unmap(sa, len, 1, len);
>      return 0;
>  }
>  #endif /* CONFIG_USER_ONLY */
> 

Looks sane to me.

Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [Qemu-devel] [PATCH v1 3/3] s390x/tcg: Save vregs to extended mchk save area

[Thomas Huth]

On 22/02/2019 09.11, David Hildenbrand wrote:
> If we have vector registers and the designation is not zero, we have
> to try to write the vector registers. If the designation is zero or
> if storing fails, we must not indicate validity. s390_build_validity_mcic()
> automatically already sets validity if the vector instruction facility
> is installed.
> 
> As long as we don't support the guarded-storage facility, the alignemnt &
> size of the area is always 1024 bytes.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
>  target/s390x/excp_helper.c | 46 ++++++++++++++++++++++++++++++++++++--
>  target/s390x/internal.h    |  4 +++-
>  2 files changed, 47 insertions(+), 3 deletions(-)

Looks also sane to me.

Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [Qemu-devel] [PATCH v1 0/3] s390x: SIGP + IRQ preparations for TCG vector register support

[Cornelia Huck]

On Fri, 22 Feb 2019 09:11:50 +0100
David Hildenbrand <david@redhat.com> wrote:

> These are minor preparations for vector instruction support for TCG, also
> touching KVM code.
> 
> During SIGP STORE ADDITIONAL STATUS we have to properly convert the
> endianess. On machine checks, we have to also store the vector registers
> into the extended save area.
> 
> Both changes are not used by TCG code before we implement + enable
> vector instructions. KVM code shares the SIGP STORE ADDITIONAL STATUS
> implementation.
> 
> Note: Vector registers (128 bit) are modeled as two 64 bit values. Low and
> high 64 bit values correspond on big/little systems, however the values
> themself need conversion. Documentation for that will be added along with
> the actual vector instruction support.
> 
> David Hildenbrand (3):
>   s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS
>   s390x: use a QEMU-style typedef + name for SIGP save area struct
>   s390x/tcg: Save vregs to extended mchk save area
> 
>  target/s390x/excp_helper.c | 46 ++++++++++++++++++++++++++++++++++++--
>  target/s390x/helper.c      | 39 ++++++++++++++++++++------------
>  target/s390x/internal.h    |  4 +++-
>  3 files changed, 72 insertions(+), 17 deletions(-)
> 

Quick question: Unlike your floating-point patch series, this does not
depend on anything not going through the s390x tree, right?

Re: [Qemu-devel] [PATCH v1 3/3] s390x/tcg: Save vregs to extended mchk save area

[Cornelia Huck]

On Fri, 22 Feb 2019 09:11:53 +0100
David Hildenbrand <david@redhat.com> wrote:

> If we have vector registers and the designation is not zero, we have
> to try to write the vector registers. If the designation is zero or
> if storing fails, we must not indicate validity. s390_build_validity_mcic()
> automatically already sets validity if the vector instruction facility
> is installed.
> 
> As long as we don't support the guarded-storage facility, the alignemnt &
> size of the area is always 1024 bytes.

s/alignemnt & size/alignment and size/

Can change while applying.

> 
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
>  target/s390x/excp_helper.c | 46 ++++++++++++++++++++++++++++++++++++--
>  target/s390x/internal.h    |  4 +++-
>  2 files changed, 47 insertions(+), 3 deletions(-)

Re: [Qemu-devel] [PATCH v1 0/3] s390x: SIGP + IRQ preparations for TCG vector register support

[David Hildenbrand]

On 22.02.19 11:16, Cornelia Huck wrote:
> On Fri, 22 Feb 2019 09:11:50 +0100
> David Hildenbrand <david@redhat.com> wrote:
> 
>> These are minor preparations for vector instruction support for TCG, also
>> touching KVM code.
>>
>> During SIGP STORE ADDITIONAL STATUS we have to properly convert the
>> endianess. On machine checks, we have to also store the vector registers
>> into the extended save area.
>>
>> Both changes are not used by TCG code before we implement + enable
>> vector instructions. KVM code shares the SIGP STORE ADDITIONAL STATUS
>> implementation.
>>
>> Note: Vector registers (128 bit) are modeled as two 64 bit values. Low and
>> high 64 bit values correspond on big/little systems, however the values
>> themself need conversion. Documentation for that will be added along with
>> the actual vector instruction support.
>>
>> David Hildenbrand (3):
>>   s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS
>>   s390x: use a QEMU-style typedef + name for SIGP save area struct
>>   s390x/tcg: Save vregs to extended mchk save area
>>
>>  target/s390x/excp_helper.c | 46 ++++++++++++++++++++++++++++++++++++--
>>  target/s390x/helper.c      | 39 ++++++++++++++++++++------------
>>  target/s390x/internal.h    |  4 +++-
>>  3 files changed, 72 insertions(+), 17 deletions(-)
>>
> 
> Quick question: Unlike your floating-point patch series, this does not
> depend on anything not going through the s390x tree, right?
> 

While these patches are based on the others, they should apply and work
just nicely without the floating-point patches.

-- 

Thanks,

David / dhildenb

Re: [Qemu-devel] [PATCH v1 1/3] s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS

[Christian Borntraeger]

On 22.02.2019 09:11, David Hildenbrand wrote:
> As we will support vector instructions soon, and vector registers are
> stored in 64bit host chunks, let's use cpu_to_be64. Same applies to the
> guarded storage control block.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>

looks sane.

Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com>

> ---
>  target/s390x/helper.c | 31 +++++++++++++++++++++----------
>  1 file changed, 21 insertions(+), 10 deletions(-)
> 
> diff --git a/target/s390x/helper.c b/target/s390x/helper.c
> index 3d74836a83..f3fcf96482 100644
> --- a/target/s390x/helper.c
> +++ b/target/s390x/helper.c
> @@ -272,32 +272,43 @@ int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
>      return 0;
>  }
>  
> -#define ADTL_GS_OFFSET   1024 /* offset of GS data in adtl save area */
> +typedef struct SigpAdtlSaveArea {
> +    uint64_t    vregs[32][2];                     /* 0x0000 */
> +    uint8_t     pad_0x0200[0x0400 - 0x0200];      /* 0x0200 */
> +    uint64_t    gscb[4];                          /* 0x0400 */
> +    uint8_t     pad_0x0420[0x1000 - 0x0420];      /* 0x0420 */
> +} SigpAdtlSaveArea;
> +QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096);
> +
>  #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
>  int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
>  {
> +    SigpAdtlSaveArea *sa;
>      hwaddr save = len;
> -    void *mem;
> +    int i;
>  
> -    mem = cpu_physical_memory_map(addr, &save, 1);
> -    if (!mem) {
> +    sa = cpu_physical_memory_map(addr, &save, 1);
> +    if (!sa) {
>          return -EFAULT;
>      }
>      if (save != len) {
> -        cpu_physical_memory_unmap(mem, len, 1, 0);
> +        cpu_physical_memory_unmap(sa, len, 1, 0);
>          return -EFAULT;
>      }
>  
> -    /* FIXME: as soon as TCG supports these features, convert cpu->be */
>      if (s390_has_feat(S390_FEAT_VECTOR)) {
> -        memcpy(mem, &cpu->env.vregs, 512);
> +        for (i = 0; i < 32; i++) {
> +            sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0].ll);
> +            sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1].ll);
> +        }
>      }
>      if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
> -        memcpy(mem + ADTL_GS_OFFSET, &cpu->env.gscb, 32);
> +        for (i = 0; i < 4; i++) {
> +            sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]);
> +        }
>      }
>  
> -    cpu_physical_memory_unmap(mem, len, 1, len);
> -
> +    cpu_physical_memory_unmap(sa, len, 1, len);
>      return 0;
>  }
>  #endif /* CONFIG_USER_ONLY */
> 

Re: [Qemu-devel] [qemu-s390x] [PATCH v1 2/3] s390x: use a QEMU-style typedef + name for SIGP save area struct

[Christian Borntraeger]

On 22.02.2019 09:11, David Hildenbrand wrote:
> Convert this to QEMU style.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>

Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>

> ---
>  target/s390x/helper.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/s390x/helper.c b/target/s390x/helper.c
> index f3fcf96482..a7edd5df7d 100644
> --- a/target/s390x/helper.c
> +++ b/target/s390x/helper.c
> @@ -211,7 +211,7 @@ void s390_cpu_recompute_watchpoints(CPUState *cs)
>      }
>  }
>  
> -struct sigp_save_area {
> +typedef struct SigpSaveArea {
>      uint64_t    fprs[16];                       /* 0x0000 */
>      uint64_t    grs[16];                        /* 0x0080 */
>      PSW         psw;                            /* 0x0100 */
> @@ -225,13 +225,13 @@ struct sigp_save_area {
>      uint8_t     pad_0x0138[0x0140 - 0x0138];    /* 0x0138 */
>      uint32_t    ars[16];                        /* 0x0140 */
>      uint64_t    crs[16];                        /* 0x0384 */
> -};
> -QEMU_BUILD_BUG_ON(sizeof(struct sigp_save_area) != 512);
> +} SigpSaveArea;
> +QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512);
>  
>  int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
>  {
>      static const uint8_t ar_id = 1;
> -    struct sigp_save_area *sa;
> +    SigpSaveArea *sa;
>      hwaddr len = sizeof(*sa);
>      int i;
>  
> 

Re: [Qemu-devel] [PATCH v1 0/3] s390x: SIGP + IRQ preparations for TCG vector register support

[Cornelia Huck]

On Fri, 22 Feb 2019 09:11:50 +0100
David Hildenbrand <david@redhat.com> wrote:

> These are minor preparations for vector instruction support for TCG, also
> touching KVM code.
> 
> During SIGP STORE ADDITIONAL STATUS we have to properly convert the
> endianess. On machine checks, we have to also store the vector registers
> into the extended save area.
> 
> Both changes are not used by TCG code before we implement + enable
> vector instructions. KVM code shares the SIGP STORE ADDITIONAL STATUS
> implementation.
> 
> Note: Vector registers (128 bit) are modeled as two 64 bit values. Low and
> high 64 bit values correspond on big/little systems, however the values
> themself need conversion. Documentation for that will be added along with
> the actual vector instruction support.
> 
> David Hildenbrand (3):
>   s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS
>   s390x: use a QEMU-style typedef + name for SIGP save area struct
>   s390x/tcg: Save vregs to extended mchk save area
> 
>  target/s390x/excp_helper.c | 46 ++++++++++++++++++++++++++++++++++++--
>  target/s390x/helper.c      | 39 ++++++++++++++++++++------------
>  target/s390x/internal.h    |  4 +++-
>  3 files changed, 72 insertions(+), 17 deletions(-)
> 

Thanks, applied.