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[88.21.202.62]) by smtp.gmail.com with ESMTPSA id g5sm7538266wmf.37.2019.11.08.06.36.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Nov 2019 06:36:53 -0800 (PST) Subject: Re: [PATCH 2/3] hw/mips/gt64xxx: Remove dynamic field width from trace event To: qemu-devel@nongnu.org, Eric Blake References: <20191108142613.26649-1-philmd@redhat.com> <20191108142613.26649-3-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <5cffe2ac-634e-5ede-8c2a-b54ee7900464@redhat.com> Date: Fri, 8 Nov 2019 15:36:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191108142613.26649-3-philmd@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Aleksandar Markovic , qemu-block@nongnu.org, qemu-trivial@nongnu.org, Max Reitz , Stefan Hajnoczi , Aleksandar Rikalo , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/8/19 3:26 PM, Philippe Mathieu-Daud=C3=A9 wrote: > Since not all trace backends support dynamic field width in > format (dtrace via stap does not), replace by a static field > width instead. >=20 > Reported-by: Eric Blake > Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/mips/gt64xxx_pci.c | 34 +++++++++++++++++----------------- > hw/mips/trace-events | 4 ++-- > 2 files changed, 19 insertions(+), 19 deletions(-) >=20 > diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c > index 5cab9c1ee1..f427793360 100644 > --- a/hw/mips/gt64xxx_pci.c > +++ b/hw/mips/gt64xxx_pci.c > @@ -464,7 +464,7 @@ static void gt64120_writel(void *opaque, hwaddr add= r, > qemu_log_mask(LOG_GUEST_ERROR, > "gt64120: Read-only register write " > "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); Wrong replacement :( I'll respin. > break; > =20 > /* CPU Sync Barrier */ > @@ -474,7 +474,7 @@ static void gt64120_writel(void *opaque, hwaddr add= r, > qemu_log_mask(LOG_GUEST_ERROR, > "gt64120: Read-only register write " > "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); > break; > =20 > /* SDRAM and Device Address Decode */ > @@ -516,7 +516,7 @@ static void gt64120_writel(void *opaque, hwaddr add= r, > qemu_log_mask(LOG_UNIMP, > "gt64120: Unimplemented device register write " > "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); > break; > =20 > /* ECC */ > @@ -529,7 +529,7 @@ static void gt64120_writel(void *opaque, hwaddr add= r, > qemu_log_mask(LOG_GUEST_ERROR, > "gt64120: Read-only register write " > "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); > break; > =20 > /* DMA Record */ > @@ -566,7 +566,7 @@ static void gt64120_writel(void *opaque, hwaddr add= r, > qemu_log_mask(LOG_UNIMP, > "gt64120: Unimplemented DMA register write " > "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); > break; > =20 > /* Timer/Counter */ > @@ -579,7 +579,7 @@ static void gt64120_writel(void *opaque, hwaddr add= r, > qemu_log_mask(LOG_UNIMP, > "gt64120: Unimplemented timer register write " > "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); > break; > =20 > /* PCI Internal */ > @@ -623,7 +623,7 @@ static void gt64120_writel(void *opaque, hwaddr add= r, > qemu_log_mask(LOG_UNIMP, > "gt64120: Unimplemented timer register write " > "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); > break; > case GT_PCI0_CFGADDR: > phb->config_reg =3D val & 0x80fffffc; > @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr a= ddr, > /* not really implemented */ > s->regs[saddr] =3D ~(~(s->regs[saddr]) | ~(val & 0xfffffffe))= ; > s->regs[saddr] |=3D !!(s->regs[saddr] & 0xfffffffe); > - trace_gt64120_write("INTRCAUSE", size << 1, val); > + trace_gt64120_write("INTRCAUSE", size << 3, val); > break; > case GT_INTRMASK: > s->regs[saddr] =3D val & 0x3c3ffffe; > - trace_gt64120_write("INTRMASK", size << 1, val); > + trace_gt64120_write("INTRMASK", size << 3, val); > break; > case GT_PCI0_ICMASK: > s->regs[saddr] =3D val & 0x03fffffe; > - trace_gt64120_write("ICMASK", size << 1, val); > + trace_gt64120_write("ICMASK", size << 3, val); > break; > case GT_PCI0_SERR0MASK: > s->regs[saddr] =3D val & 0x0000003f; > - trace_gt64120_write("SERR0MASK", size << 1, val); > + trace_gt64120_write("SERR0MASK", size << 3, val); > break; > =20 > /* Reserved when only PCI_0 is configured. */ > @@ -683,7 +683,7 @@ static void gt64120_writel(void *opaque, hwaddr add= r, > qemu_log_mask(LOG_GUEST_ERROR, > "gt64120: Illegal register write " > "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); > break; > } > } > @@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque, > /* Interrupts */ > case GT_INTRCAUSE: > val =3D s->regs[saddr]; > - trace_gt64120_read("INTRCAUSE", size << 1, val); > + trace_gt64120_read("INTRCAUSE", size << 3, val); > break; > case GT_INTRMASK: > val =3D s->regs[saddr]; > - trace_gt64120_read("INTRMASK", size << 1, val); > + trace_gt64120_read("INTRMASK", size << 3, val); > break; > case GT_PCI0_ICMASK: > val =3D s->regs[saddr]; > - trace_gt64120_read("ICMASK", size << 1, val); > + trace_gt64120_read("ICMASK", size << 3, val); > break; > case GT_PCI0_SERR0MASK: > val =3D s->regs[saddr]; > - trace_gt64120_read("SERR0MASK", size << 1, val); > + trace_gt64120_read("SERR0MASK", size << 3, val); > break; > =20 > /* Reserved when only PCI_0 is configured. */ > @@ -960,7 +960,7 @@ static uint64_t gt64120_readl(void *opaque, > qemu_log_mask(LOG_GUEST_ERROR, > "gt64120: Illegal register read " > "reg:0x03%x size:%u value:0x%0*x\n", > - saddr << 2, size, size << 1, val); > + saddr << 2, size, size << 3, val); > break; > } > =20 > diff --git a/hw/mips/trace-events b/hw/mips/trace-events > index 75d4c73f2e..86a0213c77 100644 > --- a/hw/mips/trace-events > +++ b/hw/mips/trace-events > @@ -1,4 +1,4 @@ > # gt64xxx.c > -gt64120_read(const char *regname, int width, uint64_t value) "gt64120 = read %s value:0x%0*" PRIx64 > -gt64120_write(const char *regname, int width, uint64_t value) "gt64120= write %s value:0x%0*" PRIx64 > +gt64120_read(const char *regname, int width, uint64_t value) "gt64120 = read %s width:%d value:0x%08" PRIx64 > +gt64120_write(const char *regname, int width, uint64_t value) "gt64120= write %s width:%d value:0x%08" PRIx64 > gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t = to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%= 08" PRIx64 "@0x%08" PRIx64 >=20