From: Richard Henderson <richard.henderson@linaro.org>
To: Max Chou <max.chou@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [RFC PATCH 2/3] target/riscv: rvv: Add Zvqdotq support
Date: Tue, 2 Sep 2025 15:38:41 +0200 [thread overview]
Message-ID: <5d0fe741-9063-441d-8abc-3bb0662c1fbe@linaro.org> (raw)
In-Reply-To: <20250901133815.1693077-3-max.chou@sifive.com>
On 9/1/25 23:38, Max Chou wrote:
> +#define OPMVV_VQDOTQ(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2) \
> +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
> +{ \
> + int idx; \
> + T1 r1; \
> + T2 r2; \
> + TX1 *r1_buf = (TX1 *)vs1 + HD(i); \
> + TX2 *r2_buf = (TX2 *)vs2 + HD(i); \
> + TD acc = *((TD *)vd + HD(i)); \
> + int64_t partial_sum = 0; \
I think it's clear partial_sum should be the 32-bit type TD.
Indeed, I'm not sure why you don't just have
TD acc = ((TD *)vd)[HD(i)];
> + \
> + for (idx = 0; idx < 4; ++idx) { \
> + r1 = *((T1 *)r1_buf + HS1(idx)); \
> + r2 = *((T2 *)r2_buf + HS2(idx)); \
> + partial_sum += (r1 * r2); \
acc += r1 * r2;
> + } \
> + *((TD *)vd + HD(i)) = (acc + partial_sum) & MAKE_64BIT_MASK(0, 32); \
((TD *)vd)[HD(i)] = acc;
because that final mask is bogus.
r~
> +}
> +
> +RVVCALL(OPMVV_VQDOTQ, vqdot_vv, QOP_SSS_B, H4, H1, H1)
> +RVVCALL(OPMVV_VQDOTQ, vqdotu_vv, QOP_UUU_B, H4, H1, H1)
> +RVVCALL(OPMVV_VQDOTQ, vqdotsu_vv, QOP_SUS_B, H4, H1, H1)
next prev parent reply other threads:[~2025-09-02 13:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-01 13:38 [RFC PATCH 0/3] Support RISC-V Zvqdotq vector dot-product extension Max Chou
2025-09-01 13:38 ` [RFC PATCH 1/3] target/riscv: Add Zvqdotq cfg property Max Chou
2025-09-01 13:38 ` [RFC PATCH 2/3] target/riscv: rvv: Add Zvqdotq support Max Chou
2025-09-02 13:38 ` Richard Henderson [this message]
2025-09-03 0:26 ` Max Chou
2025-09-03 3:43 ` Richard Henderson
2025-09-03 12:43 ` Max Chou
2025-09-01 13:38 ` [RFC PATCH 3/3] target/riscv: Expose Zvqdotq extension as a cpu property Max Chou
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