From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94B79C433B4 for ; Tue, 6 Apr 2021 02:39:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA36161353 for ; Tue, 6 Apr 2021 02:39:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EA36161353 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:37830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTbcj-0001iG-V3 for qemu-devel@archiver.kernel.org; Mon, 05 Apr 2021 22:39:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTbaV-0000pX-Vo for qemu-devel@nongnu.org; Mon, 05 Apr 2021 22:37:08 -0400 Received: from mga06.intel.com ([134.134.136.31]:62837) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTbaR-00022N-U4 for qemu-devel@nongnu.org; Mon, 05 Apr 2021 22:37:07 -0400 IronPort-SDR: A8EuBcWjxc6tzUWIG7gfIaUxHoP5h51IQb8HTuPGrOGWajDFKZGWcwWE770AqnaO9M4siFBWd2 wwI0JdfSDzEw== X-IronPort-AV: E=McAfee;i="6000,8403,9945"; a="254300013" X-IronPort-AV: E=Sophos;i="5.81,308,1610438400"; d="scan'208";a="254300013" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2021 19:36:56 -0700 IronPort-SDR: HfbcOsrte4aTyNUjwDviJjf+gLlZUPOdmhsaxNuUhGJLRnoc12mvR7jxfVrz1X2lgspM4pv+KQ GH77gXKVmvug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,308,1610438400"; d="scan'208";a="380743556" Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga006.jf.intel.com with ESMTP; 05 Apr 2021 19:36:54 -0700 Message-ID: <5d31c441a2318c6dd969da8ddcff81e083c48e80.camel@linux.intel.com> Subject: Re: [PATCH v4] i386/cpu_dump: support AVX512 ZMM regs dump From: Robert Hoo To: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com Date: Tue, 06 Apr 2021 10:36:53 +0800 In-Reply-To: References: <1616770469-36979-1-git-send-email-robert.hu@linux.intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Received-SPF: none client-ip=134.134.136.31; envelope-from=robert.hu@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, Ping... Thanks On Fri, 2021-03-26 at 23:01 +0800, Robert Hoo wrote: > On Fri, 2021-03-26 at 22:54 +0800, Robert Hoo wrote: > > Since commit fa4518741e (target-i386: Rename struct XMMReg to > > ZMMReg), > > CPUX86State.xmm_regs[] has already been extended to 512bit to > > support > > AVX512. > > Also, other qemu level supports for AVX512 registers are there for > > years. > > But in x86_cpu_dump_state(), still only dump XMM registers no > > matter > > YMM/ZMM is enabled. > > This patch is to complement this, let it dump XMM/YMM/ZMM > > accordingly. > > > > Signed-off-by: Robert Hoo > > --- > > Changelog: > > v4: stringent AVX512 case and AVX case judgement criteria > > v3: fix some coding style issue. > > v2: dump XMM/YMM/ZMM according to XSAVE state-components > > enablement. > > > > target/i386/cpu-dump.c | 62 ++++++++++++++++++++++++++++++++++++++ > > ------------ > > 1 file changed, 47 insertions(+), 15 deletions(-) > > > > diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c > > index aac21f1..dea4564 100644 > > --- a/target/i386/cpu-dump.c > > +++ b/target/i386/cpu-dump.c > > @@ -478,6 +478,11 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, > > int flags) > > qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer); > > if (flags & CPU_DUMP_FPU) { > > int fptag; > > + const uint64_t avx512_mask = XSTATE_OPMASK_MASK | \ > > + XSTATE_ZMM_Hi256_MASK | \ > > + XSTATE_Hi16_ZMM_MASK | \ > > + XSTATE_YMM_MASK | > > XSTATE_SSE_MASK, > > + avx_mask = XSTATE_YMM_MASK | > > XSTATE_SSE_MASK; > > fptag = 0; > > for(i = 0; i < 8; i++) { > > fptag |= ((!env->fptags[i]) << i); > > @@ -499,21 +504,48 @@ void x86_cpu_dump_state(CPUState *cs, FILE > > *f, > > int flags) > > else > > qemu_fprintf(f, " "); > > } > > - if (env->hflags & HF_CS64_MASK) > > - nb = 16; > > - else > > - nb = 8; > > - for(i=0;i > - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", > > - i, > > - env->xmm_regs[i].ZMM_L(3), > > - env->xmm_regs[i].ZMM_L(2), > > - env->xmm_regs[i].ZMM_L(1), > > - env->xmm_regs[i].ZMM_L(0)); > > - if ((i & 1) == 1) > > - qemu_fprintf(f, "\n"); > > - else > > - qemu_fprintf(f, " "); > > + > > + if ((env->xcr0 & avx512_mask) == avx512_mask) { > > + /* XSAVE enabled AVX512 */ > > + for (i = 0; i < NB_OPMASK_REGS; i++) { > > + qemu_fprintf(f, "Opmask%02d=%016lx%s", i, env- > > > opmask_regs[i], > > > > + ((i & 3) == 3) ? "\n" : " "); > > + } > > + > > + nb = (env->hflags & HF_CS64_MASK) ? 32 : 8; > > + for (i = 0; i < nb; i++) { > > + qemu_fprintf(f, "ZMM%02d=%016lx %016lx %016lx > > %016lx > > %016lx " > > + "%016lx %016lx %016lx\n", > > + i, > > + env->xmm_regs[i].ZMM_Q(7), > > + env->xmm_regs[i].ZMM_Q(6), > > + env->xmm_regs[i].ZMM_Q(5), > > + env->xmm_regs[i].ZMM_Q(4), > > + env->xmm_regs[i].ZMM_Q(3), > > + env->xmm_regs[i].ZMM_Q(2), > > + env->xmm_regs[i].ZMM_Q(1), > > + env->xmm_regs[i].ZMM_Q(0)); > > + } > > + } else if (env->xcr0 & avx_mask) { > > Here should be > else if ((env->xcr0 & avx_mask) == avx_mask) > > Sorry about my sleepy head. > > > + /* XSAVE enabled AVX */ > > + nb = env->hflags & HF_CS64_MASK ? 16 : 8; > > + for (i = 0; i < nb; i++) { > > + qemu_fprintf(f, "YMM%02d=%016lx %016lx %016lx > > %016lx\n", > > + i, > > + env->xmm_regs[i].ZMM_Q(3), > > + env->xmm_regs[i].ZMM_Q(2), > > + env->xmm_regs[i].ZMM_Q(1), > > + env->xmm_regs[i].ZMM_Q(0)); > > + } > > + } else { /* SSE and below cases */ > > + nb = env->hflags & HF_CS64_MASK ? 16 : 8; > > + for (i = 0; i < nb; i++) { > > + qemu_fprintf(f, "XMM%02d=%016lx %016lx%s", > > + i, > > + env->xmm_regs[i].ZMM_Q(1), > > + env->xmm_regs[i].ZMM_Q(0), > > + (i & 1) ? "\n" : " "); > > + } > > } > > } > > if (flags & CPU_DUMP_CODE) {