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([2602:47:d49d:ec01:bc82:8006:f19e:85e]) by smtp.gmail.com with ESMTPSA id e126-20020a621e84000000b005360da6b26bsm13224618pfe.159.2022.10.06.11.53.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Oct 2022 11:53:45 -0700 (PDT) Message-ID: <5d3984c4-54c3-463b-4595-361c5e65e43d@linaro.org> Date: Thu, 6 Oct 2022 11:53:43 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v3 23/42] target/arm: Use probe_access_full for BTI Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20221001162318.153420-1-richard.henderson@linaro.org> <20221001162318.153420-24-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.435, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/6/22 07:57, Peter Maydell wrote: > On Sat, 1 Oct 2022 at 17:38, Richard Henderson > wrote: >> >> Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit. >> In is_guarded_page, use probe_access_full instead of just guessing >> that the tlb entry is still present. Also handles the FIXME about >> executing from device memory. >> >> Signed-off-by: Richard Henderson >> --- >> target/arm/cpu-param.h | 8 ++++---- >> target/arm/cpu.h | 13 ------------- >> target/arm/internals.h | 1 + >> target/arm/ptw.c | 7 ++++--- >> target/arm/translate-a64.c | 22 ++++++++-------------- >> 5 files changed, 17 insertions(+), 34 deletions(-) >> >> diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h >> index 118ca0e5c0..689a9645dc 100644 >> --- a/target/arm/cpu-param.h >> +++ b/target/arm/cpu-param.h >> @@ -32,12 +32,12 @@ >> # define TARGET_PAGE_BITS_MIN 10 >> >> /* >> - * Cache the attrs and sharability fields from the page table entry. >> + * Cache the attrs, sharability, and gp fields from the page table entry. >> */ >> # define TARGET_PAGE_ENTRY_EXTRA \ >> - uint8_t pte_attrs; \ >> - uint8_t shareability; >> - >> + uint8_t pte_attrs; \ >> + uint8_t shareability; \ >> + bool guarded; > > I notice this now brings this very close to just having an ARMCacheAttrs > struct in it (in fact it's going to be one byte bigger than the ARMCachettrs). > But it's probably better to keep them separate since we care a lot more > about keeping the TLB entry small I suppose. I kept them as separate fields like this for simplicity. Since CPUTLBEntryFull is 4 or 8-byte aligned (depending on the host), the structure still has 1 or 5 bytes of padding after the addition of this bool. >> - /* >> - * We test this immediately after reading an insn, which means >> - * that any normal page must be in the TLB. The only exception >> - * would be for executing from flash or device memory, which >> - * does not retain the TLB entry. >> - * >> - * FIXME: Assume false for those, for now. We could use >> - * arm_cpu_get_phys_page_attrs_debug to re-read the page >> - * table entry even for that case. >> - */ > > I think we should keep at least some of this comment: the part > about the reason we can assert that probe_access_full() doesn't > return TLB_INVALID being that we tested immediately after the > insn read is still true, right? Yes. r~