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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id mp16-20020a170902fd1000b001db7e461d8asm9381989plb.130.2024.03.04.20.34.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Mar 2024 20:34:46 -0800 (PST) Message-ID: <5d3c7aa7-16d2-4812-a72b-dae5e567b9b8@linaro.org> Date: Mon, 4 Mar 2024 18:34:42 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 1/1] target/loongarch: Fixed tlb huge page loading issue Content-Language: en-US To: Xianglai Li , qemu-devel@nongnu.org Cc: maobibo@loongson.cn, Song Gao , Xiaojuan Yang , zhaotianrui@loongson.cn References: <5b23421ee1ebf59142c7d7a3bc1082fff910f2fa.1709610311.git.lixianglai@loongson.cn> From: Richard Henderson In-Reply-To: <5b23421ee1ebf59142c7d7a3bc1082fff910f2fa.1709610311.git.lixianglai@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/4/24 17:51, Xianglai Li wrote: > When we use qemu tcg simulation, the page size of bios is 4KB. > When using the level 2 super large page (page size is 1G) to create the page table, > it is found that the content of the corresponding address space is abnormal, > resulting in the bios can not start the operating system and graphical interface normally. > > The lddir and ldpte instruction emulation has > a problem with the use of super large page processing above level 2. > The page size is not correctly calculated, > resulting in the wrong page size of the table entry found by tlb. > > Signed-off-by: Xianglai Li > Cc: maobibo@loongson.cn > Cc: Song Gao > Cc: Xiaojuan Yang > Cc: zhaotianrui@loongson.cn > --- > target/loongarch/cpu.h | 1 + > target/loongarch/tcg/tlb_helper.c | 21 ++++++++++++--------- > 2 files changed, 13 insertions(+), 9 deletions(-) > > diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h > index ec37579fd6..eab3e41c71 100644 > --- a/target/loongarch/cpu.h > +++ b/target/loongarch/cpu.h > @@ -292,6 +292,7 @@ typedef struct CPUArchState { > uint32_t fcsr0_mask; > > uint32_t cpucfg[21]; > + uint32_t lddir_ps; This magical cpu state does not appear in the manual. Are you sure that large pages above level 2 are really supported by LDDIR? Some explanation from the hardware engineering side is required. r~