From: "Cédric Le Goater" <clg@kaod.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Zheyu Ma" <zheyuma97@gmail.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v3] hw/gpio/aspeed: Add reg_table_size to AspeedGPIOClass
Date: Thu, 20 Jun 2024 14:35:02 +0200 [thread overview]
Message-ID: <5d617ff8-dc3d-4126-8466-ed1596d3389d@kaod.org> (raw)
In-Reply-To: <f446fdbf-90f2-4d07-8f1f-06b697ec8c01@linaro.org>
>> @@ -75,6 +75,7 @@ struct AspeedGPIOClass {
>> uint32_t nr_gpio_pins;
>> uint32_t nr_gpio_sets;
>> const AspeedGPIOReg *reg_table;
>> + uint32_t reg_table_size;
>> };
>
> - "reg_table_size" is a number of registers, using s/size/count/ might
> be clearer.
> - No point in specifying 32-bit, "unsigned" is sufficient.
>
> (Cédric, if you agree, you might update your tree).
>
> Unrelated to this patch but figured out while reviewing, in
> aspeed_gpio_read/write 'idx' is
> - pointlessly assigned to -1
> - of type 'uint64_t', also pointless, 'unsigned' is clearer.
Zheyu, could you please send a v4 ? Thanks,
C.
next prev parent reply other threads:[~2024-06-20 12:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-19 18:36 [PATCH v3] hw/gpio/aspeed: Add reg_table_size to AspeedGPIOClass Zheyu Ma
2024-06-19 23:48 ` Andrew Jeffery
2024-06-20 5:44 ` Cédric Le Goater
2024-06-20 11:09 ` Philippe Mathieu-Daudé
2024-06-20 12:35 ` Cédric Le Goater [this message]
2024-06-20 14:03 ` Zheyu Ma
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