From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LPNIF-0007Jd-1K for qemu-devel@nongnu.org; Tue, 20 Jan 2009 15:33:51 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LPNID-0007Gk-3q for qemu-devel@nongnu.org; Tue, 20 Jan 2009 15:33:50 -0500 Received: from [199.232.76.173] (port=42650 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LPNIC-0007GR-Sp for qemu-devel@nongnu.org; Tue, 20 Jan 2009 15:33:48 -0500 Received: from mail-qy0-f20.google.com ([209.85.221.20]:39139) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LPNIC-0003xp-HQ for qemu-devel@nongnu.org; Tue, 20 Jan 2009 15:33:48 -0500 Received: by qyk13 with SMTP id 13so5033710qyk.10 for ; Tue, 20 Jan 2009 12:33:47 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <497632E1.3050707@redhat.com> References: <1232477465-32386-1-git-send-email-glommer@redhat.com> <1232477465-32386-2-git-send-email-glommer@redhat.com> <1232477465-32386-3-git-send-email-glommer@redhat.com> <1232477465-32386-4-git-send-email-glommer@redhat.com> <1232477465-32386-5-git-send-email-glommer@redhat.com> <497632E1.3050707@redhat.com> Date: Tue, 20 Jan 2009 18:33:39 -0200 Message-ID: <5d6222a80901201233m6a2894f3p2a2a62865455901a@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH 4/6] replace cpu_physical_memory_rw From: Glauber Costa Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com On Tue, Jan 20, 2009 at 6:24 PM, Avi Kivity wrote: > Glauber Costa wrote: >> >> This patch introduces a kvm version of cpu_physical_memory_rw. >> The main motivation is to bypass tcg version, which contains >> tcg-specific code, as well as data structures not used by kvm, >> such as l1_phys_map. >> >> In this patch, I'm using a runtime selection of which function >> to call, but the mid-term goal is to use function pointers in >> a way very close to which QEMUAccel used to be. >> > > You will need to trivially adjust this for cpu_physical_memory_map(). Was it merged yet? > > You're still allocating the page descriptors, right? By page descriptors you mean the l1_phys_map? If so, yes, because of the way cpu_exec works. We can live without them right now. With other patches I have queued up, we get closer to this goal. > > My feeling is that qemu could long term drop phys_ram_base and move to a > slot based structure; most lookups will hit on the first access (the largest > slot). The main motivation is to enable memory hotplug. Of course this > shouldn't interfere with this patchset going in. > -- Glauber Costa. "Free as in Freedom" http://glommer.net "The less confident you are, the more serious you have to act."