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[83.11.37.15]) by smtp.gmail.com with ESMTPSA id i23-20020a17090671d700b00a52222f2b21sm421900ejk.66.2024.05.02.03.56.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 May 2024 03:56:22 -0700 (PDT) Message-ID: <5da6dcc6-2c00-483f-bf33-cbeb3d931f2e@linaro.org> Date: Thu, 2 May 2024 12:56:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT To: Peter Maydell Cc: Richard Henderson , Dorjoy Chowdhury , qemu-devel@nongnu.org, Leif Lindholm References: <20240419183135.12276-1-dorjoychy111@gmail.com> <753b3a55-9589-4dcb-b656-8b3025e847df@linaro.org> From: Marcin Juszkiewicz Content-Language: pl-PL, en-GB, en-HK Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=marcin.juszkiewicz@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org W dniu 2.05.2024 o 12:37, Peter Maydell pisze: >> * what are the constraints on the Aff* fields (eg that kernel >> commit suggests Aff0 shouldn't be > 15)? > This one is apparently related to GICv3 -- if the GIC doesn't > implement RangeSelector support in ICC_SGI0R_EL1 and other > places (advertised via GICD_TYPER.RSS and ICC_CTLR_EL1.SS) then > there's no way to send an SGI to a CPU whose Aff0 is outside > [0..15], and so you shouldn't build a system with Aff0 > 15. > QEMU's GICv3 doesn't implement the RSS functionality (though it > wouldn't be hard to add if we really cared), so we should also > keep Aff0 in [0..15]. Arm/virt uses 8 cores/cluster on GICv2 and 16 cores/cluster on GICv3 as this is amount of SGI target-list bits available. Arm/sbsa-ref goes with 8 cores per cluster by use of ARM_DEFAULT_CPUS_PER_CLUSTER. > We have ARM_DEFAULT_CPUS_PER_CLUSTER = 8, which does keep us > in that range. I don't think there's really a good reason for > it to be 8 rather than 16: this might be legacy from GICv2? GICv2 supported only 8 cores.