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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id u18-20020a056a00099200b004f737cdd046sm7848732pfg.145.2022.03.17.12.31.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Mar 2022 12:31:35 -0700 (PDT) Message-ID: <5dc9f996-44a6-cead-8e41-42ab9ef720ee@linaro.org> Date: Thu, 17 Mar 2022 12:31:33 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH for-7.1 v6 41/51] target/nios2: Introduce shadow register sets Content-Language: en-US To: Peter Maydell References: <20220317050538.924111-1-richard.henderson@linaro.org> <20220317050538.924111-42-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, amir.gonnen@neuroblade.ai, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/17/22 11:33, Peter Maydell wrote: > The behaviour of r0 in the shadow register sets is definitely > underspecified, but I really don't believe that r0 is a normal > writeable register for everything except the crs=0 set, which > is what you've implemented here. My best guess is: > * registers are implemented as a pile of RAM, including r0 > * on reset the set-0 r0 is reset to 0, but nothing else is > (this bit's actually in the spec) > * writes to r0 are always discarded, except for the special > case of wrprs Thanks for the insight. It certainly sounds plausible. > I'm tempted to suggest we should make our tbflags bit > "we know r0 is zero" -- the guest doesn't have many ways > to switch register set, basically I think just eret and taking > an external interrupt, and those either happen outside the > TB or are going to end the TB anyway. Can we make > cpu_get_tb_cpu_state() simply set the TB flag if > env->shadow_regs[crs][0] == 0 > or have I missed something that means that won't work? Yes, this is easy. > (I actually wouldn't care to bet much money on wrprs being > unable to write to register-set-0 r0. It would be interesting > to test that on the real hardware.) Indeed. I'm tempted to treat them all the same. r~