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Tue, 21 Mar 2023 09:15:07 +0000 Received: from BY5PR11MB4500.namprd11.prod.outlook.com ([fe80::68a4:ef95:6726:3fc5]) by BY5PR11MB4500.namprd11.prod.outlook.com ([fe80::68a4:ef95:6726:3fc5%4]) with mapi id 15.20.6178.037; Tue, 21 Mar 2023 09:15:07 +0000 Message-ID: <5e358d79-76be-b230-194c-a25ffad324c2@intel.com> Date: Tue, 21 Mar 2023 17:14:56 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change Content-Language: en-US To: liweiwei CC: LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Bin Meng , Daniel Henrique Barboza , "open list:RISC-V TCG CPUs" , "open list:All patches CC here" References: <20230321063746.151107-1-fei2.wu@intel.com> <8029cbcf-520f-cfd3-5b5a-923685a1da80@iscas.ac.cn> From: "Wu, Fei" In-Reply-To: <8029cbcf-520f-cfd3-5b5a-923685a1da80@iscas.ac.cn> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SG2PR03CA0088.apcprd03.prod.outlook.com (2603:1096:4:7c::16) To BY5PR11MB4500.namprd11.prod.outlook.com (2603:10b6:a03:1c3::24) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY5PR11MB4500:EE_|SA1PR11MB6760:EE_ X-MS-Office365-Filtering-Correlation-Id: 578cab6b-ca23-49c6-e2f2-08db29ecc345 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=fei2.wu@intel.com; helo=mga07.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/21/2023 4:50 PM, liweiwei wrote: > > On 2023/3/21 16:40, Wu, Fei wrote: >> On 3/21/2023 4:28 PM, liweiwei wrote: >>> On 2023/3/21 14:37, fei2.wu@intel.com wrote: >>>> From: Fei Wu >>>> >>>> Kernel needs to access user mode memory e.g. during syscalls, the >>>> window >>>> is usually opened up for a very limited time through MSTATUS.SUM, the >>>> overhead is too much if tlb_flush() gets called for every SUM change. >>>> This patch saves addresses accessed when SUM=1, and flushs only these >>>> pages when SUM changes to 0. If the buffer is not large enough to save >>>> all the pages during SUM=1, it will fall back to tlb_flush when >>>> necessary. >>>> >>>> The buffer size is set to 4 since in this MSTATUS.SUM open-up window, >>>> most of the time kernel accesses 1 or 2 pages, it's very rare to see >>>> more than 4 pages accessed. >>>> >>>> It's not necessary to save/restore these new added status, as >>>> tlb_flush() is always called after restore. >>>> >>>> Result of 'pipe 10' from unixbench boosts from 223656 to 1327407. Many >>>> other syscalls benefit a lot from this one too. >>>> >>>> Signed-off-by: Fei Wu >>>> Reviewed-by: LIU Zhiwei >>>> --- >>>>    target/riscv/cpu.h        |  4 ++++ >>>>    target/riscv/cpu_helper.c |  7 +++++++ >>>>    target/riscv/csr.c        | 14 +++++++++++++- >>>>    3 files changed, 24 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >>>> index 638e47c75a..926dbce59f 100644 >>>> --- a/target/riscv/cpu.h >>>> +++ b/target/riscv/cpu.h >>>> @@ -383,6 +383,10 @@ struct CPUArchState { >>>>        uint64_t kvm_timer_compare; >>>>        uint64_t kvm_timer_state; >>>>        uint64_t kvm_timer_frequency; >>>> + >>>> +#define MAX_CACHED_SUM_U_ADDR_NUM 4 >>>> +    uint64_t sum_u_count; >>>> +    uint64_t sum_u_addr[MAX_CACHED_SUM_U_ADDR_NUM]; >>>>    }; >>>>      OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) >>>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >>>> index f88c503cf4..5ad0418eb6 100644 >>>> --- a/target/riscv/cpu_helper.c >>>> +++ b/target/riscv/cpu_helper.c >>>> @@ -1068,6 +1068,13 @@ restart: >>>>                        (access_type == MMU_DATA_STORE || (pte & >>>> PTE_D))) { >>>>                    *prot |= PAGE_WRITE; >>>>                } >>>> +            if ((pte & PTE_U) && (mode & PRV_S) && >>>> +                    get_field(env->mstatus, MSTATUS_SUM)) { >>>> +                if (env->sum_u_count < MAX_CACHED_SUM_U_ADDR_NUM) { >>>> +                    env->sum_u_addr[env->sum_u_count] = addr; >>>> +                } >>>> +                ++env->sum_u_count; >>>> +            } >>>>                return TRANSLATE_SUCCESS; >>>>            } >>>>        } >>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >>>> index ab566639e5..74b7638c8a 100644 >>>> --- a/target/riscv/csr.c >>>> +++ b/target/riscv/csr.c >>>> @@ -1246,9 +1246,21 @@ static RISCVException >>>> write_mstatus(CPURISCVState *env, int csrno, >>>>          /* flush tlb on mstatus fields that affect VM */ >>>>        if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | >>>> -            MSTATUS_MPRV | MSTATUS_SUM)) { >>>> +            MSTATUS_MPRV)) { >>>>            tlb_flush(env_cpu(env)); >>>> +        env->sum_u_count = 0; >>>> +    } else if ((mstatus & MSTATUS_SUM) && !(val & MSTATUS_SUM)) { >>>> +        if (env->sum_u_count > MAX_CACHED_SUM_U_ADDR_NUM) { >>>> +            tlb_flush(env_cpu(env)); >>>> +        } else { >>>> +            for (int i = 0; i < env->sum_u_count; ++i) { >>>> +                tlb_flush_page_by_mmuidx(env_cpu(env), >>>> env->sum_u_addr[i], >>>> +                                         1 << PRV_S | 1 << PRV_M); >>>> +            } >>>> +        } >>>> +        env->sum_u_count = 0; >>>>        } >>> Whether tlb should  be flushed when SUM is changed from 0 to 1? >>> >> When SUM is changed from 0 to 1, all the existing tlb entries remain >> valid as the permission is elevated instead of reduced, so I don't think >> it's necessary to flush tlb. > > If elevated not unchanged, I think the tlb also needs update, since new > permitted access rights may be added to the tlb. > Assume the following flow, if the new rights have been added to tlb during SUM=0, they're visible and still valid after setting SUM=1 again. Could you please add a specific counter example in this flow? enable uaccess (set SUM = 1) ... (access user mem from S mode) disable uaccess (set SUM = 0) ... (update TLB_SUM_0) <-- flush tlb or not right before enabling uaccess? enable uaccess (set SUM = 1) <-- okay to access TLB_SUM_0? disable uaccess (set SUM = 0) Thanks, Fei. > Regards, > > Weiwei Li > >> >> Thanks, >> Fei. >> >>> Regards, >>> >>> Weiwei Li >>> >>>> + >>>>        mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | >>>>            MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | >>>>            MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | >