From: Richard Henderson <richard.henderson@linaro.org>
To: Mikael Szreder <git@miszr.win>, qemu-devel@nongnu.org
Cc: Artyom Tarasenko <atar4qemu@gmail.com>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: Re: [PATCH v2] target/sparc: Fix gdbstub incorrectly handling registers f32-f62
Date: Sat, 15 Feb 2025 11:58:09 -0800 [thread overview]
Message-ID: <5e9d9e51-1950-45d5-9580-9f1072e3b1b4@linaro.org> (raw)
In-Reply-To: <20250214070343.11501-1-git@miszr.win>
On 2/13/25 23:03, Mikael Szreder wrote:
> The gdbstub implementation for the Sparc architecture would
> incorrectly calculate the the floating point register offset.
> This resulted in, for example, registers f32 and f34 to point to
> the same value.
>
> The issue was caused by the confusion between even register numbers
> and even register indexes. For example, the register index of f32 is 64
> and f34 is 65.
>
> Fixes: 30038fd81808 ("target-sparc: Change fpr representation to doubles.")
> Signed-off-by: Mikael Szreder <git@miszr.win>
> ---
> target/sparc/gdbstub.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
> index ec0036e9ef..134617fb23 100644
> --- a/target/sparc/gdbstub.c
> +++ b/target/sparc/gdbstub.c
> @@ -79,8 +79,13 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> }
> }
> if (n < 80) {
> - /* f32-f62 (double width, even numbers only) */
> - return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll);
> + /* f32-f62 (16 double width registers, even register numbers only)
> + * n == 64: f32 : env->fpr[16]
> + * n == 65: f34 : env->fpr[17]
> + * etc...
> + * n == 79: f62 : env->fpr[31]
> + */
> + return gdb_get_reg64(mem_buf, env->fpr[(n - 64) + 16].ll);
> }
> switch (n) {
> case 80:
> @@ -173,8 +178,13 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> }
> return 4;
> } else if (n < 80) {
> - /* f32-f62 (double width, even numbers only) */
> - env->fpr[(n - 32) / 2].ll = tmp;
> + /* f32-f62 (16 double width registers, even register numbers only)
> + * n == 64: f32 : env->fpr[16]
> + * n == 65: f34 : env->fpr[17]
> + * etc...
> + * n == 79: f62 : env->fpr[31]
> + */
> + env->fpr[(n - 64) + 16].ll = tmp;
> } else {
> switch (n) {
> case 80:
Queued, thanks.
r~
next prev parent reply other threads:[~2025-02-15 19:58 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-14 7:03 [PATCH v2] target/sparc: Fix gdbstub incorrectly handling registers f32-f62 Mikael Szreder
2025-02-14 15:54 ` Richard Henderson
2025-02-15 19:58 ` Richard Henderson [this message]
2025-02-17 4:54 ` Mikael Szreder
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