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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id k7-20020a63ff07000000b00372dc67e854sm644517pgi.14.2022.02.24.16.52.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Feb 2022 16:52:10 -0800 (PST) Message-ID: <5ec03bd3-f077-83cc-7fb1-fcfa4b991668@linaro.org> Date: Thu, 24 Feb 2022 14:52:07 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH] accel/tcg/cpu-exec: fix precise single-stepping after interrupt Content-Language: en-US From: Richard Henderson To: Luc Michel , qemu-devel@nongnu.org References: <20220214132656.11397-1-lmichel@kalray.eu> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/24/22 14:23, Richard Henderson wrote: > On 2/14/22 03:26, Luc Michel wrote: >> In some cases, cpu->exit_request can be false after handling the >> interrupt, leading to another TB being executed instead of returning >> to the main loop. >> >> Fix this by returning true unconditionally when in single-step mode. >> >> Fixes: ba3c35d9c4026361fd380b269dc6def9510b7166 >> >> Signed-off-by: Luc Michel >> --- >> Coming back on this issue I worked on with Richard in 2020. The issue is >> that when debugging the guest with GDB, the first instruction of the IRQ >> handler is missed by GDB (it's still executed though). >> >> It happened to me again in TCG RR mode (but not in MTTCG). It seems that >> cpu->exit_request can be false in RR mode when returning from >> cc->tcg_ops->cpu_exec_interrupt, leading to cpu_handle_interrupt >> returning false and the next TB being executed, instead of the EXCP_DEBUG >> being handled. >> --- >>   accel/tcg/cpu-exec.c | 10 +++++++--- >>   1 file changed, 7 insertions(+), 3 deletions(-) >> >> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c >> index 8b4cd6c59d..74d7f83f34 100644 >> --- a/accel/tcg/cpu-exec.c >> +++ b/accel/tcg/cpu-exec.c >> @@ -796,13 +796,17 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, >>                   /* >>                    * After processing the interrupt, ensure an EXCP_DEBUG is >>                    * raised when single-stepping so that GDB doesn't miss the >>                    * next instruction. >>                    */ >> -                cpu->exception_index = >> -                    (cpu->singlestep_enabled ? EXCP_DEBUG : -1); >> -                *last_tb = NULL; >> +                if (unlikely(cpu->singlestep_enabled)) { >> +                    cpu->exception_index = EXCP_DEBUG; >> +                    return true; > > By returning here, you also need to qemu_mutex_unlock_iothread(). > >> +                } else { > > You can remove the else after the return. > Otherwise this looks good; sorry for the delay. I'll just fix this up when applying, it's minor enough. r~