From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 104C1C02198 for ; Tue, 18 Feb 2025 09:18:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tkJjb-0001Dv-Hv; Tue, 18 Feb 2025 04:17:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tkJjM-0001C1-PG; Tue, 18 Feb 2025 04:17:30 -0500 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tkJjJ-0007E8-NI; Tue, 18 Feb 2025 04:17:28 -0500 Received: from mail.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4Yxv751gCwz4wcm; Tue, 18 Feb 2025 20:17:21 +1100 (AEDT) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (Client did not present a certificate) by mail.ozlabs.org (Postfix) with ESMTPSA id 4Yxv723VVPz4wb0; Tue, 18 Feb 2025 20:17:18 +1100 (AEDT) Message-ID: <5ec569c6-f7a7-4a0d-b60e-abb727cf1330@kaod.org> Date: Tue, 18 Feb 2025 10:17:16 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 11/28] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication To: Jamin Lin , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , "open list:All patches CC here" , "open list:ASPEED BMCs" Cc: troy_lee@aspeedtech.com References: <20250213033531.3367697-1-jamin_lin@aspeedtech.com> <20250213033531.3367697-12-jamin_lin@aspeedtech.com> Content-Language: en-US, fr From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Autocrypt: addr=clg@kaod.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=OI5l=VJ=kaod.org=clg@ozlabs.org; helo=mail.ozlabs.org X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/13/25 04:35, Jamin Lin wrote: > The behavior of the INTC set IRQ is almost identical between INTC and INTCIO. > To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function > to handle both INTC and INTCIO IRQ behavior. It's good practice to add "No functional change". Reviewed-by: Cédric Le Goater Thanks, C. > Signed-off-by: Jamin Lin > --- > hw/intc/aspeed_intc.c | 62 ++++++++++++++++++++++++------------------- > 1 file changed, 34 insertions(+), 28 deletions(-) > > diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c > index 59c1069294..fd4f75805a 100644 > --- a/hw/intc/aspeed_intc.c > +++ b/hw/intc/aspeed_intc.c > @@ -92,11 +92,40 @@ static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx, > qemu_set_irq(s->output_pins[outpin_idx], level); > } > > +static void aspeed_intc_set_irq_handler(AspeedINTCState *s, > + const AspeedINTCIRQ *intc_irq, > + uint32_t select) > +{ > + const char *name = object_get_typename(OBJECT(s)); > + > + if (s->mask[intc_irq->inpin_idx] || s->regs[intc_irq->status_addr]) { > + /* > + * a. mask is not 0 means in ISR mode > + * sources interrupt routine are executing. > + * b. status register value is not 0 means previous > + * source interrupt does not be executed, yet. > + * > + * save source interrupt to pending variable. > + */ > + s->pending[intc_irq->inpin_idx] |= select; > + trace_aspeed_intc_pending_irq(name, intc_irq->inpin_idx, > + s->pending[intc_irq->inpin_idx]); > + } else { > + /* > + * notify firmware which source interrupt are coming > + * by setting status register > + */ > + s->regs[intc_irq->status_addr] = select; > + trace_aspeed_intc_trigger_irq(name, intc_irq->inpin_idx, > + intc_irq->outpin_idx, > + s->regs[intc_irq->status_addr]); > + aspeed_intc_update(s, intc_irq->inpin_idx, intc_irq->outpin_idx, 1); > + } > +} > + > /* > - * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804. > - * Utilize "address & 0x0f00" to get the irq and irq output pin index > - * The value of irq should be 0 to num_inpins. > - * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on. > + * GICINT128 to GICINT136 map 1:1 to input and output IRQs 0 to 8. > + * The value of input IRQ should be between 0 and the number of inputs. > */ > static void aspeed_intc_set_irq(void *opaque, int irq, int level) > { > @@ -135,30 +164,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level) > } > > trace_aspeed_intc_select(name, select); > - > - if (s->mask[intc_irq->inpin_idx] || s->regs[intc_irq->status_addr]) { > - /* > - * a. mask is not 0 means in ISR mode > - * sources interrupt routine are executing. > - * b. status register value is not 0 means previous > - * source interrupt does not be executed, yet. > - * > - * save source interrupt to pending variable. > - */ > - s->pending[intc_irq->inpin_idx] |= select; > - trace_aspeed_intc_pending_irq(name, intc_irq->inpin_idx, > - s->pending[intc_irq->inpin_idx]); > - } else { > - /* > - * notify firmware which source interrupt are coming > - * by setting status register > - */ > - s->regs[intc_irq->status_addr] = select; > - trace_aspeed_intc_trigger_irq(name, intc_irq->inpin_idx, > - intc_irq->outpin_idx, > - s->regs[intc_irq->status_addr]); > - aspeed_intc_update(s, intc_irq->inpin_idx, intc_irq->outpin_idx, 1); > - } > + aspeed_intc_set_irq_handler(s, intc_irq, select); > } > > static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,