From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: Re: [PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class
Date: Mon, 28 Apr 2025 07:58:46 -0700 [thread overview]
Message-ID: <5ecee8bf-c340-4d7e-b47b-461c80ee9bfa@linaro.org> (raw)
In-Reply-To: <30770d2b-ac76-4d13-b8f2-ca39c0b82e0f@ventanamicro.com>
On 4/28/25 04:50, Daniel Henrique Barboza wrote:
>> static const TypeInfo riscv_kvm_cpu_type_infos[] = {
>> {
>> .name = TYPE_RISCV_CPU_HOST,
>> .parent = TYPE_RISCV_CPU,
>> - .class_init = riscv_host_cpu_class_init,
>> +#if defined(TARGET_RISCV32)
>> + .class_data = &((const RISCVCPUDef) {
>> + .misa_mxl_max = MXL_RV32,
>> + },
>> +#elif defined(TARGET_RISCV64)
>> + .class_data = &((const RISCVCPUDef) {
>> + .misa_mxl_max = MXL_RV64,
>> + },
>> +#endif
>> }
>> };
>
> Are we sure this patch compiles? As I said in the v3 this except opening 2 parentheses
> and closing just one after RISCVCPUDef:
>
>
>> - .class_init = riscv_host_cpu_class_init,
>> +#if defined(TARGET_RISCV32)
>> + .class_data = &(( <-----
> const RISCVCPUDef) {
I'll repeat that the parenthesis are completely unnecessary, just
= &(const RISCVCPUDef){ ... }
The extras should be dropped everywhere.
r~
next prev parent reply other threads:[~2025-04-28 14:59 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-28 7:34 [PATCH v4 00/26] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-04-28 7:34 ` [PATCH 01/26] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-04-28 7:34 ` [PATCH 02/26] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-04-28 7:34 ` [PATCH 03/26] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-04-28 7:34 ` [PATCH 04/26] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-04-28 7:34 ` [PATCH 05/26] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-04-28 7:34 ` [PATCH 06/26] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-04-28 7:34 ` [PATCH 07/26] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-04-28 7:34 ` [PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-04-28 11:50 ` Daniel Henrique Barboza
2025-04-28 12:17 ` Paolo Bonzini
2025-04-28 15:20 ` Philippe Mathieu-Daudé
2025-04-28 19:26 ` Paolo Bonzini
2025-04-28 14:58 ` Richard Henderson [this message]
2025-04-28 7:34 ` [PATCH 09/26] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-04-28 7:34 ` [PATCH 10/26] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-04-28 7:34 ` [PATCH 11/26] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-04-28 7:34 ` [PATCH 12/26] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-04-28 7:34 ` [PATCH 13/26] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-04-28 7:34 ` [PATCH 14/26] target/riscv: convert profile CPU models " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 15/26] target/riscv: convert bare " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 16/26] target/riscv: convert dynamic " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 17/26] target/riscv: convert SiFive E " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 18/26] target/riscv: convert ibex " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 19/26] target/riscv: convert SiFive U " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 20/26] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-04-28 7:34 ` [PATCH 21/26] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-04-28 7:34 ` [PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-04-29 4:23 ` Joel Stanley
2025-04-28 7:34 ` [PATCH 23/26] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 24/26] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 25/26] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 26/26] target/riscv: remove .instance_post_init Paolo Bonzini
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