From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Mayuresh Chitale <mchitale@ventanamicro.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com
Subject: Re: [PATCH v6 5/5] target/riscv: smstateen knobs
Date: Fri, 22 Jul 2022 09:47:35 +0800 [thread overview]
Message-ID: <5eda3670-f818-0a3b-8ab3-345ed258ab60@iscas.ac.cn> (raw)
In-Reply-To: <20220721153136.377578-6-mchitale@ventanamicro.com>
在 2022/7/21 下午11:31, Mayuresh Chitale 写道:
> Add knobs to allow users to enable smstateen and also export it via the
> ISA extension string.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db2b8e4d30..2b7ed95396 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -98,6 +98,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
> ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
> ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
> + ISA_EXT_DATA_ENTRY(smstateen, true, PRIV_VERSION_1_12_0, ext_smstateen),
> ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
> @@ -987,6 +988,7 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> + DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
prev parent reply other threads:[~2022-07-22 1:48 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-21 15:31 [PATCH v6 0/5] RISC-V Smstateen support Mayuresh Chitale
2022-07-21 15:31 ` [PATCH v6 1/5] target/riscv: Add smstateen support Mayuresh Chitale
2022-07-22 0:31 ` Weiwei Li
2022-07-24 15:39 ` Mayuresh Chitale
2022-07-25 7:11 ` Weiwei Li
2022-07-28 5:39 ` Mayuresh Chitale
2022-07-21 15:31 ` [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg Mayuresh Chitale
2022-07-22 0:45 ` Weiwei Li
2022-07-28 6:41 ` Mayuresh Chitale
2022-07-28 7:59 ` Weiwei Li
2022-07-21 15:31 ` [PATCH v6 3/5] target/riscv: smstateen check for fcsr Mayuresh Chitale
2022-07-22 1:42 ` Weiwei Li
2022-07-24 15:49 ` Mayuresh Chitale
2022-07-25 7:23 ` Weiwei Li
2022-07-28 6:15 ` Mayuresh Chitale
2022-07-28 7:38 ` Weiwei Li
2022-07-28 8:09 ` Ben Dooks
2022-07-29 12:29 ` Mayuresh Chitale
2022-07-21 15:31 ` [PATCH v6 4/5] target/riscv: smstateen check for AIA/IMSIC Mayuresh Chitale
2022-07-22 1:45 ` Weiwei Li
2022-07-21 15:31 ` [PATCH v6 5/5] target/riscv: smstateen knobs Mayuresh Chitale
2022-07-22 1:47 ` Weiwei Li [this message]
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