From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>, qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/54] riscv-to-apply queue
Date: Mon, 10 Jul 2023 23:59:06 +0100 [thread overview]
Message-ID: <5edaf40e-e503-cfcf-d1d6-f5064d409bfa@linaro.org> (raw)
In-Reply-To: <20230710123205.2441106-1-alistair.francis@wdc.com>
On 7/10/23 13:31, Alistair Francis wrote:
> The following changes since commit fcb237e64f9d026c03d635579c7b288d0008a6e5:
>
> Merge tag 'pull-vfio-20230710' ofhttps://github.com/legoater/qemu into staging (2023-07-10 09:17:06 +0100)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230710-1
>
> for you to fetch changes up to a47842d16653b4f73b5d56ff0c252dd8a329481b:
>
> riscv: Add support for the Zfa extension (2023-07-10 22:29:20 +1000)
>
> ----------------------------------------------------------------
> Third RISC-V PR for 8.1
>
> * Use xl instead of mxl for disassemble
> * Factor out extension tests to cpu_cfg.h
> * disas/riscv: Add vendor extension support
> * disas/riscv: Add support for XVentanaCondOps
> * disas/riscv: Add support for XThead* instructions
> * Fix mstatus related problems
> * Fix veyron-v1 CPU properties
> * Fix the xlen for data address when MPRV=1
> * opensbi: Upgrade from v1.2 to v1.3
> * Enable 32-bit Spike OpenSBI boot testing
> * Support the watchdog timer of HiFive 1 rev b
> * Only build qemu-system-riscv$$ on rv$$ host
> * Add RVV registers to log
> * Restrict ACLINT to TCG
> * Add syscall riscv_hwprobe
> * Add support for BF16 extensions
> * KVM_RISCV_SET_TIMER macro is not configured correctly
> * Generate devicetree only after machine initialization is complete
> * virt: Convert fdt_load_addr to uint64_t
> * KVM: fixes and enhancements
> * Add support for the Zfa extension
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
next prev parent reply other threads:[~2023-07-10 23:00 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 12:31 [PULL 00/54] riscv-to-apply queue Alistair Francis
2023-07-10 12:31 ` [PULL 01/54] target/riscv: Use xl instead of mxl for disassemble Alistair Francis
2023-07-10 12:31 ` [PULL 02/54] target/riscv: Factor out extension tests to cpu_cfg.h Alistair Francis
2023-07-10 12:31 ` [PULL 03/54] disas/riscv: Move types/constants to new header file Alistair Francis
2023-07-10 12:31 ` [PULL 04/54] disas/riscv: Make rv_op_illegal a shared enum value Alistair Francis
2023-07-10 12:31 ` [PULL 05/54] disas/riscv: Encapsulate opcode_data into decode Alistair Francis
2023-07-10 12:31 ` [PULL 06/54] disas/riscv: Provide infrastructure for vendor extensions Alistair Francis
2023-07-10 12:31 ` [PULL 07/54] disas/riscv: Add support for XVentanaCondOps Alistair Francis
2023-07-10 12:31 ` [PULL 08/54] disas/riscv: Add support for XThead* instructions Alistair Francis
2023-07-10 12:31 ` [PULL 09/54] target/riscv: Make MPV only work when MPP != PRV_M Alistair Francis
2023-07-10 12:31 ` [PULL 10/54] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled Alistair Francis
2023-07-10 12:31 ` [PULL 11/54] target/riscv: Remove redundant assignment to SXL Alistair Francis
2023-07-10 12:31 ` [PULL 12/54] target/riscv/cpu.c: fix veyron-v1 CPU properties Alistair Francis
2023-07-10 12:31 ` [PULL 13/54] target/riscv: Add additional xlen for address when MPRV=1 Alistair Francis
2023-07-10 12:31 ` [PULL 14/54] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV Alistair Francis
2023-07-10 12:31 ` [PULL 15/54] roms/opensbi: Upgrade from v1.2 to v1.3 Alistair Francis
2023-07-10 12:31 ` [PULL 16/54] tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing Alistair Francis
2023-07-10 12:31 ` [PULL 17/54] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b Alistair Francis
2023-07-10 12:31 ` [PULL 18/54] hw/riscv: sifive_e: " Alistair Francis
2023-07-10 12:31 ` [PULL 19/54] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e Alistair Francis
2023-07-10 12:31 ` [PULL 20/54] target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson Alistair Francis
2023-07-10 12:31 ` [PULL 21/54] target/riscv: Only build KVM guest with same wordsize as host Alistair Francis
2023-07-10 12:31 ` [PULL 22/54] target/riscv: Add RVV registers to log Alistair Francis
2023-07-10 12:31 ` [PULL 23/54] hw/riscv/virt: Restrict ACLINT to TCG Alistair Francis
2023-07-10 12:31 ` [PULL 24/54] linux-user/riscv: Add syscall riscv_hwprobe Alistair Francis
2023-07-10 12:31 ` [PULL 25/54] target/riscv: Add properties for BF16 extensions Alistair Francis
2023-07-10 12:31 ` [PULL 26/54] target/riscv: Add support for Zfbfmin extension Alistair Francis
2023-07-10 12:31 ` [PULL 27/54] target/riscv: Add support for Zvfbfmin extension Alistair Francis
2023-07-10 12:31 ` [PULL 28/54] target/riscv: Add support for Zvfbfwma extension Alistair Francis
2023-07-10 12:31 ` [PULL 29/54] target/riscv: Expose properties for BF16 extensions Alistair Francis
2023-07-10 12:31 ` [PULL 30/54] target/riscv: Set the correct exception for implict G-stage translation fail Alistair Francis
2023-07-10 12:31 ` [PULL 31/54] target/riscv: Add disas support for BF16 extensions Alistair Francis
2023-07-10 12:31 ` [PULL 32/54] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly Alistair Francis
2023-07-10 12:31 ` [PULL 33/54] riscv: Generate devicetree only after machine initialization is complete Alistair Francis
2023-07-10 12:31 ` [PULL 34/54] hw/riscv: virt: Convert fdt_load_addr to uint64_t Alistair Francis
2023-07-10 12:31 ` [PULL 35/54] target/riscv: skip features setup for KVM CPUs Alistair Francis
2023-07-10 12:31 ` [PULL 36/54] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set Alistair Francis
2023-07-10 12:31 ` [PULL 37/54] target/riscv/cpu.c: restrict 'mvendorid' value Alistair Francis
2023-07-10 12:31 ` [PULL 38/54] target/riscv/cpu.c: restrict 'mimpid' value Alistair Francis
2023-07-10 12:31 ` [PULL 39/54] target/riscv/cpu.c: restrict 'marchid' value Alistair Francis
2023-07-10 12:31 ` [PULL 40/54] target/riscv: use KVM scratch CPUs to init KVM properties Alistair Francis
2023-07-10 12:31 ` [PULL 41/54] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() Alistair Francis
2023-07-10 12:31 ` [PULL 42/54] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs Alistair Francis
2023-07-10 12:31 ` [PULL 43/54] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU Alistair Francis
2023-07-10 12:31 ` [PULL 44/54] target/riscv/cpu: add misa_ext_info_arr[] Alistair Francis
2023-07-10 12:31 ` [PULL 45/54] target/riscv: add KVM specific MISA properties Alistair Francis
2023-07-10 12:31 ` [PULL 46/54] target/riscv/kvm.c: update KVM MISA bits Alistair Francis
2023-07-10 12:31 ` [PULL 47/54] target/riscv/kvm.c: add multi-letter extension KVM properties Alistair Francis
2023-07-10 12:31 ` [PULL 48/54] target/riscv/cpu.c: add satp_mode properties earlier Alistair Francis
2023-07-10 12:32 ` [PULL 49/54] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() Alistair Francis
2023-07-10 12:32 ` [PULL 50/54] target/riscv/cpu.c: create KVM mock properties Alistair Francis
2023-07-10 12:32 ` [PULL 51/54] target/riscv: update multi-letter extension KVM properties Alistair Francis
2023-07-10 12:32 ` [PULL 52/54] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper Alistair Francis
2023-07-10 12:32 ` [PULL 53/54] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM Alistair Francis
2023-07-10 12:32 ` [PULL 54/54] riscv: Add support for the Zfa extension Alistair Francis
2023-07-10 22:59 ` Richard Henderson [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-10-12 4:09 [PULL 00/54] riscv-to-apply queue Alistair Francis
2023-10-12 18:51 ` Stefan Hajnoczi
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