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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21f3683dc55sm33238375ad.125.2025.02.07.09.22.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Feb 2025 09:22:19 -0800 (PST) Message-ID: <5ee77b8c-e6a4-421b-b729-a6535fdf1e6d@linaro.org> Date: Fri, 7 Feb 2025 09:22:17 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm/helper: Fix timer interrupt masking when HCR_EL2.E2H == 0 To: Peter Maydell , qemu-devel@nongnu.org Cc: "open list:ARM TCG CPUs" , Florian Lugou , =?UTF-8?Q?Alex_Benn=C3=A9e?= References: <20240615185423.49474-1-florian.lugou@provenrun.com> <20240620135627.qxcrkdx5v7wdurx4@flugou-latitude5401> <20240621140725.f4hsasmhrhh4joxm@flugou-latitude5401> <20240820113024.53tmzejw2omm6bbx@flugou-latitude5401> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/7/25 07:45, Peter Maydell wrote: > This is where things go wrong -- icount_start_warp_timer() > notices that all CPU threads are currently idle, and > decides it needs to warp the timer forwards to the > next deadline, which is at the end of time -- INT64_MAX. > > But once timer_mod_ns() returns, the generic timer code > is going to raise an interrupt (this goes through the GIC > code and comes back into the CPU which calls cpu_interrupt()), > so we don't want to warp the timer at all. The clock should > stay exactly at the value it has and the CPU is going to > have more work to do. > > How is this supposed to work? Shouldn't we only be doing > the "start moving the icount forward to the next deadline" > once we've completed all the "run timers and AIO stuff" that > icount_handle_deadline() triggers, not randomly in the middle > of that when this timer callback or some other one might do > something to trigger an interrupt? I don't understand timer warping at all. And you're right, it doesn't seem like this should happen outside of a specific point in the main loop. > ... But I don't think there's any reason why > timer callbacks should be obliged to reprogram their timers > last, and in any case you can imagine scenarios where there > are multiple timer callbacks for different timers and it's > only the second timer that raises an interrupt... Agreed. r~