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From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Riku Voipio <riku.voipio@iki.fi>
Subject: Re: [Qemu-devel] [PATCH] accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
Date: Sun, 20 Jan 2019 07:38:18 +1100	[thread overview]
Message-ID: <5ef47526-1794-df32-1bbe-fa29f8cd028c@linaro.org> (raw)
In-Reply-To: <20190108180014.32386-1-peter.maydell@linaro.org>

On 1/9/19 5:00 AM, Peter Maydell wrote:
> In cpu_signal_handler() for aarch64 hosts, currently we parse
> the faulting instruction to see if it is a load or a store.
> Since the 3.16 kernel (~2014), the kernel has provided us with
> the syndrome register for a fault, which includes the WnR bit.
> Use this instead if it is present, only falling back to
> instruction parsing if not.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Since I originally asked the kernel folks to add the ESR context
> so we could use it in QEMU, I figured that it was about time
> (five years later...) to write the code to make use of it.
> 
> I wanted to say "everybody surely has at least a 3.16
> kernel for aarch64 machines" and delete the fallback code,
> but it turns out that the gcc compile farm box has 3.13.0...
> ---
>  accel/tcg/user-exec.c | 66 ++++++++++++++++++++++++++++++++++---------
>  1 file changed, 52 insertions(+), 14 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

I should note that we fail to generate esr_context from aarch64-linux-user.


r~

      parent reply	other threads:[~2019-01-19 20:38 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-08 18:00 [Qemu-devel] [PATCH] accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write Peter Maydell
2019-01-18 14:29 ` Peter Maydell
2019-01-19 20:38 ` Richard Henderson [this message]

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